Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	495378	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

190564

1

T1

35

T2

25

T3

92

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	359362	1			T1	182		T2	182		T3	143
values[0x0]	162938	1			T1	34		T2	26		T3	78
values[0x1]	163642	1			T1	28		T2	36		T3	83

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	392281	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

293661

1

T1

88

T2

77

T3

140

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2119	1			T3	1		T7	35		T9	67
valid_sources[0x01]	2202	1			T5	2		T8	6		T9	47
valid_sources[0x02]	2251	1			T5	10		T6	2		T9	46
valid_sources[0x03]	2166	1			T3	4		T8	2		T9	55
valid_sources[0x04]	3650	1			T5	3		T6	1		T9	51
valid_sources[0x05]	3731	1			T5	3		T6	3		T7	346
valid_sources[0x06]	2315	1			T5	3		T8	2		T9	58
valid_sources[0x07]	4525	1			T5	7		T6	1		T7	12
valid_sources[0x08]	2606	1			T6	4		T9	61		T43	1
valid_sources[0x09]	2052	1			T3	3		T8	2		T9	44
valid_sources[0x0a]	2365	1			T2	21		T3	4		T5	6
valid_sources[0x0b]	2716	1			T9	35		T43	3		T87	2
valid_sources[0x0c]	2088	1			T5	34		T6	2		T9	44
valid_sources[0x0d]	2151	1			T3	1		T5	6		T9	62
valid_sources[0x0e]	2269	1			T3	1		T5	4		T7	13
valid_sources[0x0f]	2665	1			T5	1		T6	1		T9	36
valid_sources[0x10]	2123	1			T4	1		T5	4		T6	3
valid_sources[0x11]	2571	1			T3	1		T5	2		T8	3
valid_sources[0x12]	3179	1			T3	2		T5	1		T6	3
valid_sources[0x13]	2163	1			T7	14		T9	61		T87	1
valid_sources[0x14]	3427	1			T5	1		T9	43		T43	1
valid_sources[0x15]	2279	1			T3	1		T5	7		T6	1
valid_sources[0x16]	2565	1			T3	1		T5	3		T6	1
valid_sources[0x17]	2174	1			T5	1		T6	3		T8	3
valid_sources[0x18]	2200	1			T3	6		T5	3		T6	1
valid_sources[0x19]	3870	1			T3	1		T8	2		T9	43
valid_sources[0x1a]	2201	1			T2	13		T3	1		T7	13
valid_sources[0x1b]	3638	1			T3	1		T5	3		T7	12
valid_sources[0x1c]	2452	1			T5	4		T6	4		T7	14
valid_sources[0x1d]	5179	1			T2	6		T3	1		T6	2
valid_sources[0x1e]	2035	1			T3	1		T5	3		T7	25
valid_sources[0x1f]	2151	1			T3	3		T5	2		T9	61
valid_sources[0x20]	2787	1			T7	611		T8	2		T9	62
valid_sources[0x21]	2204	1			T3	3		T8	1		T9	52
valid_sources[0x22]	2235	1			T5	3		T7	14		T8	1
valid_sources[0x23]	2390	1			T7	2		T9	37		T43	1
valid_sources[0x24]	2261	1			T5	14		T9	42		T43	1
valid_sources[0x25]	3416	1			T5	1		T9	52		T87	1
valid_sources[0x26]	2657	1			T3	1		T5	2		T8	2
valid_sources[0x27]	2819	1			T3	1		T6	1		T9	44
valid_sources[0x28]	2098	1			T5	6		T8	2		T9	52
valid_sources[0x29]	2221	1			T5	1		T6	1		T9	45
valid_sources[0x2a]	3082	1			T3	3		T5	2		T6	1
valid_sources[0x2b]	2568	1			T5	6		T7	12		T8	1
valid_sources[0x2c]	2287	1			T5	1		T9	66		T87	1
valid_sources[0x2d]	2548	1			T3	2		T5	2		T6	2
valid_sources[0x2e]	2486	1			T2	13		T3	1		T6	2
valid_sources[0x2f]	2134	1			T3	1		T5	6		T6	4
valid_sources[0x30]	2268	1			T3	1		T6	4		T7	13
valid_sources[0x31]	2921	1			T6	1		T9	50		T43	1
valid_sources[0x32]	2660	1			T5	2		T8	1		T9	48
valid_sources[0x33]	2386	1			T3	7		T6	3		T8	2
valid_sources[0x34]	2364	1			T5	2		T9	54		T39	2
valid_sources[0x35]	2061	1			T3	3		T5	3		T8	2
valid_sources[0x36]	3089	1			T3	4		T5	10		T9	58
valid_sources[0x37]	4499	1			T6	11		T7	14		T8	1
valid_sources[0x38]	2185	1			T3	2		T5	5		T6	1
valid_sources[0x39]	2133	1			T3	4		T5	5		T6	3
valid_sources[0x3a]	3055	1			T2	22		T3	1		T5	5
valid_sources[0x3b]	3735	1			T3	3		T6	1		T7	12
valid_sources[0x3c]	2113	1			T6	1		T7	13		T8	4
valid_sources[0x3d]	2375	1			T5	4		T6	1		T7	13
valid_sources[0x3e]	2409	1			T3	2		T7	12		T9	38
valid_sources[0x3f]	2572	1			T8	1		T9	52		T87	1
valid_sources[0x40]	2219	1			T3	1		T5	6		T9	32
valid_sources[0x41]	3133	1			T3	1		T5	6		T6	4
valid_sources[0x42]	2393	1			T3	4		T5	2		T6	3
valid_sources[0x43]	2274	1			T5	14		T7	13		T8	2
valid_sources[0x44]	3503	1			T5	4		T7	365		T8	2
valid_sources[0x45]	2239	1			T3	2		T9	47		T87	1
valid_sources[0x46]	2334	1			T3	1		T5	3		T6	1
valid_sources[0x47]	2016	1			T3	2		T6	1		T8	1
valid_sources[0x48]	2266	1			T3	2		T9	66		T43	2
valid_sources[0x49]	2588	1			T3	4		T5	19		T6	3
valid_sources[0x4a]	2025	1			T3	1		T5	3		T9	61
valid_sources[0x4b]	2171	1			T5	18		T9	36		T43	2
valid_sources[0x4c]	2798	1			T3	2		T5	3		T6	3
valid_sources[0x4d]	2293	1			T6	1		T9	37		T43	2
valid_sources[0x4e]	2165	1			T6	11		T7	14		T9	29
valid_sources[0x4f]	2343	1			T3	1		T5	2		T6	2
valid_sources[0x50]	2238	1			T5	5		T8	2		T9	51
valid_sources[0x51]	2990	1			T6	1		T8	1		T9	44
valid_sources[0x52]	2888	1			T3	4		T5	2		T9	47
valid_sources[0x53]	2022	1			T9	44		T43	2		T87	5
valid_sources[0x54]	3246	1			T5	8		T8	1		T9	44
valid_sources[0x55]	2307	1			T5	12		T9	39		T43	1
valid_sources[0x56]	2402	1			T5	6		T7	17		T8	1
valid_sources[0x57]	2152	1			T3	1		T5	5		T6	1
valid_sources[0x58]	2813	1			T8	1		T9	60		T88	2
valid_sources[0x59]	2661	1			T3	2		T5	8		T6	3
valid_sources[0x5a]	1987	1			T3	2		T5	8		T6	1
valid_sources[0x5b]	2368	1			T3	3		T5	6		T8	3
valid_sources[0x5c]	2625	1			T3	3		T6	1		T7	15
valid_sources[0x5d]	2154	1			T3	6		T5	1		T8	1
valid_sources[0x5e]	2123	1			T3	2		T5	1		T7	13
valid_sources[0x5f]	2561	1			T3	6		T6	4		T9	34
valid_sources[0x60]	2607	1			T2	6		T3	3		T5	1
valid_sources[0x61]	2209	1			T3	4		T5	7		T9	73
valid_sources[0x62]	3179	1			T2	7		T3	2		T6	1
valid_sources[0x63]	2263	1			T8	1		T9	56		T87	1
valid_sources[0x64]	2193	1			T3	1		T5	6		T6	1
valid_sources[0x65]	2213	1			T2	1		T9	41		T43	2
valid_sources[0x66]	2227	1			T9	48		T14	19		T43	1
valid_sources[0x67]	2190	1			T3	2		T5	2		T7	51
valid_sources[0x68]	2099	1			T2	29		T9	44		T43	5
valid_sources[0x69]	1957	1			T3	5		T7	13		T9	43
valid_sources[0x6a]	2426	1			T5	2		T6	2		T7	15
valid_sources[0x6b]	2569	1			T3	5		T7	13		T8	1
valid_sources[0x6c]	4638	1			T3	1		T7	14		T9	34
valid_sources[0x6d]	2392	1			T3	1		T5	6		T6	4
valid_sources[0x6e]	2076	1			T3	1		T5	12		T6	1
valid_sources[0x6f]	3359	1			T5	2		T6	2		T8	5
valid_sources[0x70]	2162	1			T5	7		T7	12		T9	63
valid_sources[0x71]	2257	1			T5	1		T6	3		T9	68
valid_sources[0x72]	2292	1			T5	20		T9	41		T20	78
valid_sources[0x73]	4149	1			T3	1		T5	3		T7	13
valid_sources[0x74]	2197	1			T6	3		T9	42		T87	1
valid_sources[0x75]	2332	1			T3	2		T7	12		T8	6
valid_sources[0x76]	2056	1			T3	1		T5	2		T6	1
valid_sources[0x77]	2177	1			T3	4		T5	1		T9	64
valid_sources[0x78]	2078	1			T3	3		T9	55		T43	1
valid_sources[0x79]	2220	1			T5	5		T7	36		T9	58
valid_sources[0x7a]	2411	1			T3	2		T5	2		T9	63
valid_sources[0x7b]	2166	1			T3	1		T5	2		T6	1
valid_sources[0x7c]	2394	1			T3	1		T7	26		T9	60
valid_sources[0x7d]	2244	1			T7	36		T9	37		T43	1
valid_sources[0x7e]	2087	1			T3	1		T7	24		T9	50
valid_sources[0x7f]	2840	1			T8	1		T9	39		T39	1
valid_sources[0x80]	2681	1			T3	1		T6	2		T9	58

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

96695

1

T1

19

T2

13

T3

43

values[0x0]

all_enables

biggest_size

60691

1

T1

13

T2

9

T3

29

values[0x1]

all_enables

biggest_size

33178

1

T1

3

T2

3

T3

20