SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35057 | 1 | T5 | 266 | T35 | 395 | T36 | 409 | ||||
others[1] | 34961 | 1 | T5 | 306 | T35 | 398 | T20 | 2 | ||||
others[2] | 35093 | 1 | T5 | 292 | T35 | 405 | T36 | 423 | ||||
others[3] | 58440 | 1 | T5 | 540 | T35 | 686 | T20 | 1 | ||||
false | 18797 | 1 | T5 | 50 | T7 | 134 | T8 | 24 | ||||
true | 28573 | 1 | T1 | 1 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34682 | 1 | T5 | 303 | T35 | 368 | T20 | 1 | ||||
others[1] | 35156 | 1 | T5 | 297 | T35 | 402 | T36 | 369 | ||||
others[2] | 35201 | 1 | T5 | 322 | T35 | 424 | T36 | 418 | ||||
others[3] | 58414 | 1 | T5 | 487 | T35 | 670 | T20 | 1 | ||||
false | 12001 | 1 | T5 | 50 | T7 | 67 | T8 | 12 | ||||
true | 21841 | 1 | T1 | 1 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 650 | 1 | T1 | 4 | T2 | 4 | T6 | 5 | ||||
others[1] | 652 | 1 | T1 | 4 | T2 | 3 | T6 | 2 | ||||
others[2] | 661 | 1 | T1 | 6 | T2 | 6 | T6 | 4 | ||||
others[3] | 1164 | 1 | T1 | 9 | T2 | 11 | T6 | 10 | ||||
false | 13117 | 1 | T1 | 8 | T2 | 6 | T3 | 1 | ||||
true | 3807 | 1 | T1 | 5 | T2 | 3 | T6 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |