Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	23924902	6122	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	23924902	255340	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	23924902	9828999	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	23924902	255319	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	23924902	6122	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	23924902	255340	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	23924902	9828999	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	23924902	255319	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	6122	0	0
T5	17584	22	0	0
T6	2466	0	0	0
T7	201053	39	0	0
T8	6282	6	0	0
T9	361706	104	0	0
T10	2962	0	0	0
T11	14985	0	0	0
T14	1456	0	0	0
T20	0	15	0	0
T21	0	24	0	0
T35	0	23	0	0
T36	0	26	0	0
T37	0	23	0	0
T38	3157	0	0	0
T39	4379	0	0	0
T48	0	3	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	255340	0	0
T5	17584	565	0	0
T6	2466	0	0	0
T7	201053	1433	0	0
T8	6282	201	0	0
T9	361706	2378	0	0
T10	2962	0	0	0
T11	14985	0	0	0
T14	1456	0	0	0
T20	0	500	0	0
T21	0	559	0	0
T35	0	604	0	0
T36	0	1837	0	0
T37	0	562	0	0
T38	3157	0	0	0
T39	4379	0	0	0
T48	0	220	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	9828999	0	0
T3	7040	3019	0	0
T4	2311	0	0	0
T5	17584	7315	0	0
T6	2466	0	0	0
T7	201053	80035	0	0
T8	6282	2466	0	0
T9	361706	153450	0	0
T10	2962	0	0	0
T11	14985	0	0	0
T14	1456	759	0	0
T35	0	12937	0	0
T39	0	1835	0	0
T64	0	3840	0	0
T87	0	6066	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	255319	0	0
T5	17584	565	0	0
T6	2466	0	0	0
T7	201053	1433	0	0
T8	6282	201	0	0
T9	361706	2376	0	0
T10	2962	0	0	0
T11	14985	0	0	0
T14	1456	0	0	0
T20	0	498	0	0
T21	0	559	0	0
T35	0	604	0	0
T36	0	1837	0	0
T37	0	562	0	0
T38	3157	0	0	0
T39	4379	0	0	0
T48	0	220	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	6122	0	0
T5	17584	22	0	0
T6	2466	0	0	0
T7	201053	39	0	0
T8	6282	6	0	0
T9	361706	104	0	0
T10	2962	0	0	0
T11	14985	0	0	0
T14	1456	0	0	0
T20	0	15	0	0
T21	0	24	0	0
T35	0	23	0	0
T36	0	26	0	0
T37	0	23	0	0
T38	3157	0	0	0
T39	4379	0	0	0
T48	0	3	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	255340	0	0
T5	17584	565	0	0
T6	2466	0	0	0
T7	201053	1433	0	0
T8	6282	201	0	0
T9	361706	2378	0	0
T10	2962	0	0	0
T11	14985	0	0	0
T14	1456	0	0	0
T20	0	500	0	0
T21	0	559	0	0
T35	0	604	0	0
T36	0	1837	0	0
T37	0	562	0	0
T38	3157	0	0	0
T39	4379	0	0	0
T48	0	220	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	9828999	0	0
T3	7040	3019	0	0
T4	2311	0	0	0
T5	17584	7315	0	0
T6	2466	0	0	0
T7	201053	80035	0	0
T8	6282	2466	0	0
T9	361706	153450	0	0
T10	2962	0	0	0
T11	14985	0	0	0
T14	1456	759	0	0
T35	0	12937	0	0
T39	0	1835	0	0
T64	0	3840	0	0
T87	0	6066	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	255319	0	0
T5	17584	565	0	0
T6	2466	0	0	0
T7	201053	1433	0	0
T8	6282	201	0	0
T9	361706	2376	0	0
T10	2962	0	0	0
T11	14985	0	0	0
T14	1456	0	0	0
T20	0	498	0	0
T21	0	559	0	0
T35	0	604	0	0
T36	0	1837	0	0
T37	0	562	0	0
T38	3157	0	0	0
T39	4379	0	0	0
T48	0	220	0	0