Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24476337	14319	0	0
intr_enable_rd_A	24476337	42682	0	0
reset_en_rd_A	24476337	1440	0	0
reset_en_regwen_rd_A	24476337	1138	0	0
wake_info_capture_dis_rd_A	24476337	1231	0	0
wakeup_en_rd_A	24476337	1744	0	0
wakeup_en_regwen_rd_A	24476337	1188	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24476337	14319	0	0
T7	201053	17	0	0
T8	6282	0	0	0
T9	361706	4	0	0
T10	2962	0	0	0
T11	14985	0	0	0
T14	1456	0	0	0
T20	0	6	0	0
T23	6555	0	0	0
T38	3157	0	0	0
T39	4379	0	0	0
T42	0	52	0	0
T43	3210	0	0	0
T46	0	36	0	0
T90	0	26	0	0
T91	0	45	0	0
T133	0	20	0	0
T134	0	22	0	0
T135	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24476337	42682	0	0
T1	4203	86	0	0
T2	3244	0	0	0
T3	7040	0	0	0
T4	2311	0	0	0
T5	17584	0	0	0
T6	2466	0	0	0
T7	201053	0	0	0
T8	6282	32	0	0
T9	361706	3480	0	0
T10	2962	0	0	0
T21	0	99	0	0
T22	0	66	0	0
T35	0	182	0	0
T39	0	11	0	0
T87	0	86	0	0
T98	0	3	0	0
T100	0	42	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24476337	1440	0	0
T9	361706	5	0	0
T10	2962	0	0	0
T11	14985	0	0	0
T14	1456	0	0	0
T23	6555	0	0	0
T35	25504	0	0	0
T38	3157	0	0	0
T39	4379	0	0	0
T43	3210	0	0	0
T52	0	1	0	0
T64	10346	0	0	0
T92	0	7	0	0
T136	0	8	0	0
T137	0	9	0	0
T138	0	23	0	0
T139	0	5	0	0
T140	0	11	0	0
T141	0	12	0	0
T142	0	7	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24476337	1138	0	0
T9	361706	6	0	0
T10	2962	0	0	0
T11	14985	0	0	0
T14	1456	0	0	0
T23	6555	0	0	0
T35	25504	0	0	0
T38	3157	0	0	0
T39	4379	0	0	0
T43	3210	0	0	0
T52	0	5	0	0
T64	10346	0	0	0
T69	0	3	0	0
T92	0	5	0	0
T95	0	15	0	0
T136	0	4	0	0
T137	0	11	0	0
T138	0	20	0	0
T139	0	11	0	0
T140	0	4	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24476337	1231	0	0
T9	361706	7	0	0
T10	2962	0	0	0
T11	14985	0	0	0
T14	1456	0	0	0
T23	6555	0	0	0
T35	25504	0	0	0
T38	3157	0	0	0
T39	4379	0	0	0
T43	3210	0	0	0
T52	0	7	0	0
T64	10346	0	0	0
T69	0	14	0	0
T92	0	5	0	0
T136	0	6	0	0
T137	0	9	0	0
T138	0	12	0	0
T139	0	2	0	0
T140	0	2	0	0
T141	0	11	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24476337	1744	0	0
T9	361706	1	0	0
T10	2962	0	0	0
T11	14985	0	0	0
T14	1456	0	0	0
T23	6555	0	0	0
T35	25504	0	0	0
T38	3157	0	0	0
T39	4379	0	0	0
T43	3210	0	0	0
T52	0	5	0	0
T64	10346	0	0	0
T69	0	5	0	0
T92	0	9	0	0
T95	0	8	0	0
T137	0	5	0	0
T138	0	16	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24476337	1188	0	0
T9	361706	5	0	0
T10	2962	0	0	0
T11	14985	0	0	0
T14	1456	0	0	0
T23	6555	0	0	0
T35	25504	0	0	0
T38	3157	0	0	0
T39	4379	0	0	0
T43	3210	0	0	0
T52	0	2	0	0
T64	10346	0	0	0
T69	0	6	0	0
T77	0	23	0	0
T95	0	13	0	0
T137	0	5	0	0
T138	0	30	0	0
T140	0	4	0	0
T141	0	10	0	0
T143	0	1	0	0