Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	23924902	51834	0	0
IoStatusRise_A	23924902	57672	0	0
MainStatusFall_A	23924902	51834	0	0
MainStatusRise_A	23924902	57672	0	0
UsbStatusFall_A	23924902	35793	0	0
UsbStatusRise_A	23924902	40314	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	51834	0	0
T1	4203	5	0	0
T2	3244	3	0	0
T3	7040	16	0	0
T4	2311	0	0	0
T5	17584	92	0	0
T6	2466	4	0	0
T7	201053	562	0	0
T8	6282	22	0	0
T9	361706	1121	0	0
T10	2962	0	0	0
T11	0	1	0	0
T14	0	10	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	57672	0	0
T1	4203	6	0	0
T2	3244	4	0	0
T3	7040	17	0	0
T4	2311	4	0	0
T5	17584	93	0	0
T6	2466	5	0	0
T7	201053	624	0	0
T8	6282	24	0	0
T9	361706	1258	0	0
T10	2962	5	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	51834	0	0
T1	4203	5	0	0
T2	3244	3	0	0
T3	7040	16	0	0
T4	2311	0	0	0
T5	17584	92	0	0
T6	2466	4	0	0
T7	201053	562	0	0
T8	6282	22	0	0
T9	361706	1121	0	0
T10	2962	0	0	0
T11	0	1	0	0
T14	0	10	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	57672	0	0
T1	4203	6	0	0
T2	3244	4	0	0
T3	7040	17	0	0
T4	2311	4	0	0
T5	17584	93	0	0
T6	2466	5	0	0
T7	201053	624	0	0
T8	6282	24	0	0
T9	361706	1258	0	0
T10	2962	5	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	35793	0	0
T1	4203	5	0	0
T2	3244	3	0	0
T3	7040	13	0	0
T4	2311	0	0	0
T5	17584	42	0	0
T6	2466	4	0	0
T7	201053	410	0	0
T8	6282	7	0	0
T9	361706	827	0	0
T10	2962	0	0	0
T11	0	1	0	0
T14	0	8	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	40314	0	0
T1	4203	6	0	0
T2	3244	4	0	0
T3	7040	14	0	0
T4	2311	4	0	0
T5	17584	42	0	0
T6	2466	5	0	0
T7	201053	454	0	0
T8	6282	8	0	0
T9	361706	924	0	0
T10	2962	5	0	0