Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	23925496	5552	0	0
EscTimeoutStoppedByClReset_A	23924902	3409200	0	0
EscTimeoutTriggersReset_A	4658463	346	0	0
RomAllowActiveState_A	23924902	57305	0	0
RomAllowCheckGoodState_A	23924902	57355	0	0
RomBlockActiveState_A	23924902	26606	0	0
RomBlockCheckGoodState_A	23924902	417677	0	0
RomIntgChkDisFalse_A	23924902	23308437	0	0
RomIntgChkDisTrue_A	23924902	113709	0	0
RstreqChkEsctimeout_A	23924902	4105	0	0
RstreqChkFsmterm_A	23924902	140	0	0
RstreqChkGlbesc_A	23924902	4105	0	0
RstreqChkMainpd_A	23924902	965321	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23925496	5552	0	0
T11	14985	25	0	0
T12	15274	93	0	0
T13	0	25	0	0
T23	6555	0	0	0
T35	25505	0	0	0
T38	3157	0	0	0
T39	4379	0	0	0
T41	0	152	0	0
T43	3210	0	0	0
T64	10347	0	0	0
T87	19717	0	0	0
T88	4023	0	0	0
T101	0	271	0	0
T104	0	53	0	0
T144	0	48	0	0
T145	0	156	0	0
T146	0	21	0	0
T147	0	11	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	3409200	0	0
T1	4203	67	0	0
T2	3244	58	0	0
T3	7040	945	0	0
T4	2311	20	0	0
T5	17584	3562	0	0
T6	2466	51	0	0
T7	201053	24662	0	0
T8	6282	976	0	0
T9	361706	28276	0	0
T10	2962	26	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4658463	346	0	0
T11	1332	3	0	0
T12	365	3	0	0
T13	0	2	0	0
T23	671	0	0	0
T35	9085	0	0	0
T38	482	0	0	0
T39	409	0	0	0
T41	0	3	0	0
T43	481	0	0	0
T64	2188	0	0	0
T87	2322	0	0	0
T88	1681	0	0	0
T101	0	3	0	0
T104	0	2	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	3	0	0
T148	0	11	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	57305	0	0
T1	4203	6	0	0
T2	3244	4	0	0
T3	7040	17	0	0
T4	2311	4	0	0
T5	17584	93	0	0
T6	2466	5	0	0
T7	201053	624	0	0
T8	6282	24	0	0
T9	361706	1258	0	0
T10	2962	5	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	57355	0	0
T1	4203	6	0	0
T2	3244	4	0	0
T3	7040	17	0	0
T4	2311	4	0	0
T5	17584	93	0	0
T6	2466	5	0	0
T7	201053	624	0	0
T8	6282	24	0	0
T9	361706	1258	0	0
T10	2962	5	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	26606	0	0
T5	17584	16	0	0
T6	2466	0	0	0
T7	201053	0	0	0
T8	6282	0	0	0
T9	361706	0	0	0
T10	2962	0	0	0
T11	14985	0	0	0
T14	1456	0	0	0
T35	0	51	0	0
T38	3157	0	0	0
T39	4379	0	0	0
T47	0	194	0	0
T149	0	755	0	0
T150	0	5	0	0
T151	0	170	0	0
T152	0	12	0	0
T153	0	902	0	0
T154	0	7	0	0
T155	0	215	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	417677	0	0
T5	17584	1304	0	0
T6	2466	0	0	0
T7	201053	1539	0	0
T8	6282	275	0	0
T9	361706	4195	0	0
T10	2962	0	0	0
T11	14985	0	0	0
T14	1456	0	0	0
T20	0	509	0	0
T21	0	1292	0	0
T35	0	1222	0	0
T36	0	4196	0	0
T37	0	1311	0	0
T38	3157	0	0	0
T39	4379	0	0	0
T42	0	4519	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	23308437	0	0
T1	4203	4116	0	0
T2	3244	3187	0	0
T3	7040	6969	0	0
T4	2311	1985	0	0
T5	17584	17509	0	0
T6	2466	2367	0	0
T7	201053	196604	0	0
T8	6282	6160	0	0
T9	361706	351788	0	0
T10	2962	2555	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	113709	0	0
T5	17584	1	0	0
T6	2466	0	0	0
T7	201053	0	0	0
T8	6282	0	0	0
T9	361706	0	0	0
T10	2962	0	0	0
T11	14985	0	0	0
T14	1456	0	0	0
T21	0	546	0	0
T22	0	5043	0	0
T38	3157	0	0	0
T39	4379	0	0	0
T47	0	997	0	0
T149	0	2429	0	0
T150	0	218	0	0
T156	0	1004	0	0
T157	0	1188	0	0
T158	0	1223	0	0
T159	0	964	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	4105	0	0
T4	2311	3	0	0
T5	17584	0	0	0
T6	2466	0	0	0
T7	201053	74	0	0
T8	6282	0	0	0
T9	361706	79	0	0
T10	2962	0	0	0
T11	14985	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	1456	0	0	0
T20	0	21	0	0
T23	0	6	0	0
T38	3157	0	0	0
T40	0	6	0	0
T41	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	140	0	0
T17	12571	20	0	0
T18	0	40	0	0
T19	0	20	0	0
T24	0	20	0	0
T25	0	40	0	0
T26	997	0	0	0
T27	1750	0	0	0
T28	2389	0	0	0
T29	3310	0	0	0
T30	15855	0	0	0
T31	52399	0	0	0
T32	20261	0	0	0
T33	28352	0	0	0
T34	13370	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	4105	0	0
T4	2311	3	0	0
T5	17584	0	0	0
T6	2466	0	0	0
T7	201053	74	0	0
T8	6282	0	0	0
T9	361706	79	0	0
T10	2962	0	0	0
T11	14985	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	1456	0	0	0
T20	0	21	0	0
T23	0	6	0	0
T38	3157	0	0	0
T40	0	6	0	0
T41	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23924902	965321	0	0
T5	17584	2037	0	0
T6	2466	0	0	0
T7	201053	8101	0	0
T8	6282	432	0	0
T9	361706	7044	0	0
T10	2962	21	0	0
T11	14985	0	0	0
T14	1456	0	0	0
T20	0	2320	0	0
T23	0	306	0	0
T35	0	1751	0	0
T36	0	6600	0	0
T37	0	2132	0	0
T38	3157	0	0	0
T39	4379	0	0	0