Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	511635	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

197261

1

T1

4

T2

13

T3

207

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	368761	1			T1	16		T2	26		T3	434
values[0x0]	169594	1			T1	2		T2	7		T3	215
values[0x1]	170541	1			T1	8		T2	3		T3	237

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	405450	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

303446

1

T1

9

T2

16

T3

330

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2044	1			T3	8		T5	6		T9	1
valid_sources[0x01]	3004	1			T4	3		T5	8		T6	3
valid_sources[0x02]	3187	1			T2	1		T3	3		T4	1
valid_sources[0x03]	2601	1			T1	3		T3	11		T4	1
valid_sources[0x04]	2881	1			T3	2		T4	5		T5	6
valid_sources[0x05]	3794	1			T3	4		T4	1		T5	2
valid_sources[0x06]	3532	1			T2	2		T3	1		T4	1
valid_sources[0x07]	2129	1			T3	1		T5	8		T14	49
valid_sources[0x08]	4911	1			T3	20		T5	8		T14	38
valid_sources[0x09]	2822	1			T3	3		T4	1		T5	4
valid_sources[0x0a]	2414	1			T5	6		T14	58		T15	65
valid_sources[0x0b]	3241	1			T1	1		T3	5		T5	8
valid_sources[0x0c]	2019	1			T3	1		T5	8		T14	40
valid_sources[0x0d]	4315	1			T1	1		T3	6		T4	4
valid_sources[0x0e]	4857	1			T3	4		T4	2		T5	7
valid_sources[0x0f]	1905	1			T3	3		T5	8		T14	56
valid_sources[0x10]	3264	1			T3	4		T5	8		T14	31
valid_sources[0x11]	2550	1			T2	1		T3	10		T5	8
valid_sources[0x12]	2858	1			T3	6		T4	1		T5	8
valid_sources[0x13]	2873	1			T3	2		T4	2		T5	15
valid_sources[0x14]	3102	1			T3	2		T4	1		T5	8
valid_sources[0x15]	1972	1			T5	10		T14	40		T36	1
valid_sources[0x16]	4403	1			T3	3		T5	14		T6	1
valid_sources[0x17]	2068	1			T3	1		T5	7		T6	1
valid_sources[0x18]	2067	1			T2	1		T3	3		T5	7
valid_sources[0x19]	3102	1			T3	2		T5	5		T10	2
valid_sources[0x1a]	2326	1			T3	2		T4	1		T5	2
valid_sources[0x1b]	3331	1			T4	1		T5	2		T14	49
valid_sources[0x1c]	2776	1			T2	1		T3	9		T14	36
valid_sources[0x1d]	2075	1			T3	2		T4	1		T5	4
valid_sources[0x1e]	5294	1			T4	1		T5	6		T14	46
valid_sources[0x1f]	3517	1			T3	2		T4	3		T5	6
valid_sources[0x20]	5167	1			T3	1		T5	5		T6	1
valid_sources[0x21]	2430	1			T3	8		T4	2		T5	6
valid_sources[0x22]	2295	1			T3	3		T5	7		T14	60
valid_sources[0x23]	2578	1			T3	6		T4	3		T5	3
valid_sources[0x24]	2639	1			T5	3		T6	2		T14	38
valid_sources[0x25]	2008	1			T2	2		T3	1		T5	4
valid_sources[0x26]	3119	1			T3	1		T4	5		T5	4
valid_sources[0x27]	2082	1			T3	1		T5	7		T14	46
valid_sources[0x28]	2210	1			T3	4		T4	1		T5	7
valid_sources[0x29]	2446	1			T3	3		T4	1		T5	6
valid_sources[0x2a]	3990	1			T2	1		T3	8		T4	1
valid_sources[0x2b]	2310	1			T5	10		T14	47		T15	58
valid_sources[0x2c]	2348	1			T2	1		T3	1		T4	1
valid_sources[0x2d]	4592	1			T3	6		T4	3		T5	5
valid_sources[0x2e]	2075	1			T5	2		T6	3		T14	36
valid_sources[0x2f]	2172	1			T3	1		T5	7		T6	1
valid_sources[0x30]	1976	1			T3	3		T5	7		T6	1
valid_sources[0x31]	2056	1			T2	1		T3	1		T5	3
valid_sources[0x32]	2632	1			T1	1		T3	2		T5	8
valid_sources[0x33]	4285	1			T1	1		T2	1		T3	4
valid_sources[0x34]	2050	1			T1	1		T5	5		T6	1
valid_sources[0x35]	4780	1			T3	1		T5	6		T6	2
valid_sources[0x36]	2217	1			T3	1		T4	1		T5	5
valid_sources[0x37]	4571	1			T3	1		T4	1		T5	7
valid_sources[0x38]	1935	1			T3	2		T4	1		T5	4
valid_sources[0x39]	2078	1			T3	11		T5	2		T6	3
valid_sources[0x3a]	1955	1			T3	9		T5	7		T14	35
valid_sources[0x3b]	2753	1			T3	7		T5	7		T19	64
valid_sources[0x3c]	2328	1			T3	8		T5	7		T6	1
valid_sources[0x3d]	2601	1			T3	1		T4	2		T5	5
valid_sources[0x3e]	2104	1			T3	3		T4	2		T5	4
valid_sources[0x3f]	3270	1			T3	3		T4	1		T5	3
valid_sources[0x40]	2154	1			T1	1		T5	6		T6	1
valid_sources[0x41]	2965	1			T3	3		T5	13		T6	2
valid_sources[0x42]	2391	1			T3	5		T4	5		T5	11
valid_sources[0x43]	3181	1			T3	3		T5	6		T6	1
valid_sources[0x44]	2136	1			T3	5		T5	11		T6	1
valid_sources[0x45]	2377	1			T5	5		T6	3		T14	40
valid_sources[0x46]	2289	1			T3	6		T5	8		T6	1
valid_sources[0x47]	2307	1			T3	4		T5	7		T14	44
valid_sources[0x48]	3288	1			T3	6		T5	8		T14	37
valid_sources[0x49]	2840	1			T2	4		T3	1		T5	6
valid_sources[0x4a]	2341	1			T1	1		T3	1		T5	5
valid_sources[0x4b]	2235	1			T2	1		T3	3		T5	3
valid_sources[0x4c]	2264	1			T5	8		T6	1		T14	34
valid_sources[0x4d]	3138	1			T3	3		T5	3		T6	1
valid_sources[0x4e]	2206	1			T3	2		T5	6		T6	1
valid_sources[0x4f]	2257	1			T3	4		T5	14		T6	2
valid_sources[0x50]	2060	1			T3	3		T4	10		T5	5
valid_sources[0x51]	2947	1			T3	6		T5	6		T14	36
valid_sources[0x52]	2211	1			T3	5		T4	3		T5	5
valid_sources[0x53]	3222	1			T3	2		T5	4		T6	1
valid_sources[0x54]	1877	1			T3	1		T5	3		T6	1
valid_sources[0x55]	2407	1			T3	2		T5	7		T6	1
valid_sources[0x56]	2680	1			T3	6		T4	1		T5	8
valid_sources[0x57]	2213	1			T5	3		T14	37		T36	1
valid_sources[0x58]	2381	1			T3	4		T4	2		T5	9
valid_sources[0x59]	2261	1			T5	3		T6	1		T14	39
valid_sources[0x5a]	2623	1			T3	4		T5	4		T6	2
valid_sources[0x5b]	3368	1			T3	1		T4	1		T5	4
valid_sources[0x5c]	4967	1			T3	2		T5	5		T6	3
valid_sources[0x5d]	3569	1			T3	8		T4	3		T5	4
valid_sources[0x5e]	3507	1			T3	4		T5	7		T14	44
valid_sources[0x5f]	2640	1			T4	1		T5	3		T14	56
valid_sources[0x60]	2228	1			T3	5		T5	2		T6	2
valid_sources[0x61]	5421	1			T3	4		T5	14		T14	37
valid_sources[0x62]	2147	1			T5	6		T14	39		T36	3
valid_sources[0x63]	1852	1			T5	4		T14	37		T36	4
valid_sources[0x64]	3976	1			T3	1		T5	3		T6	2
valid_sources[0x65]	3738	1			T3	1		T5	8		T14	42
valid_sources[0x66]	5606	1			T3	1		T4	4		T5	11
valid_sources[0x67]	1904	1			T3	2		T5	8		T14	51
valid_sources[0x68]	3549	1			T3	3		T5	14		T14	44
valid_sources[0x69]	4389	1			T3	2		T5	5		T14	53
valid_sources[0x6a]	2350	1			T3	7		T5	6		T6	1
valid_sources[0x6b]	2950	1			T3	5		T4	1		T5	4
valid_sources[0x6c]	2305	1			T3	6		T5	5		T6	2
valid_sources[0x6d]	4527	1			T3	1		T5	6		T14	58
valid_sources[0x6e]	2213	1			T3	5		T5	5		T6	3
valid_sources[0x6f]	3175	1			T3	7		T5	5		T6	8
valid_sources[0x70]	1906	1			T5	7		T10	4		T14	54
valid_sources[0x71]	3177	1			T3	3		T4	3		T5	5
valid_sources[0x72]	3083	1			T3	2		T4	1		T5	8
valid_sources[0x73]	2135	1			T3	1		T5	9		T14	59
valid_sources[0x74]	2012	1			T1	1		T3	8		T5	11
valid_sources[0x75]	2914	1			T5	8		T6	4		T14	52
valid_sources[0x76]	3238	1			T5	7		T14	42		T36	1
valid_sources[0x77]	4042	1			T1	1		T3	9		T4	2
valid_sources[0x78]	3708	1			T3	11		T4	3		T5	9
valid_sources[0x79]	2078	1			T3	10		T4	1		T5	1
valid_sources[0x7a]	2057	1			T3	9		T4	2		T5	2
valid_sources[0x7b]	2280	1			T1	1		T3	3		T5	7
valid_sources[0x7c]	2517	1			T5	4		T14	47		T15	69
valid_sources[0x7d]	2315	1			T3	13		T4	2		T5	2
valid_sources[0x7e]	3401	1			T3	3		T5	5		T6	2
valid_sources[0x7f]	1970	1			T1	1		T3	7		T4	1
valid_sources[0x80]	2496	1			T3	11		T5	5		T6	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

99609

1

T1

3

T2

11

T3

100

values[0x0]

all_enables

biggest_size

63333

1

T2

2

T3

70

T4

24

values[0x1]

all_enables

biggest_size

34319

1

T1

1

T3

37

T4

12