SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34770 | 1 | T3 | 304 | T36 | 394 | T38 | 430 | ||||
others[1] | 34541 | 1 | T3 | 286 | T36 | 369 | T38 | 408 | ||||
others[2] | 34882 | 1 | T3 | 312 | T19 | 1 | T36 | 408 | ||||
others[3] | 57918 | 1 | T3 | 474 | T19 | 1 | T36 | 691 | ||||
false | 18996 | 1 | T3 | 50 | T5 | 46 | T19 | 1 | ||||
true | 28984 | 1 | T1 | 1 | T2 | 1 | T3 | 51 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34659 | 1 | T3 | 297 | T36 | 399 | T38 | 389 | ||||
others[1] | 34743 | 1 | T3 | 285 | T36 | 393 | T38 | 391 | ||||
others[2] | 34783 | 1 | T3 | 311 | T36 | 400 | T38 | 395 | ||||
others[3] | 57814 | 1 | T3 | 512 | T19 | 1 | T36 | 668 | ||||
false | 12083 | 1 | T3 | 50 | T5 | 23 | T19 | 3 | ||||
true | 22138 | 1 | T1 | 1 | T2 | 1 | T3 | 51 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 668 | 1 | T6 | 4 | T14 | 6 | T15 | 16 | ||||
others[1] | 621 | 1 | T5 | 2 | T6 | 6 | T14 | 2 | ||||
others[2] | 670 | 1 | T5 | 3 | T6 | 4 | T19 | 1 | ||||
others[3] | 1165 | 1 | T5 | 6 | T6 | 8 | T14 | 15 | ||||
false | 13239 | 1 | T1 | 1 | T2 | 1 | T3 | 1 | ||||
true | 3729 | 1 | T5 | 22 | T6 | 1 | T19 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |