Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25919705	15229	0	0
intr_enable_rd_A	25919705	41013	0	0
reset_en_rd_A	25919705	772	0	0
reset_en_regwen_rd_A	25919705	759	0	0
wake_info_capture_dis_rd_A	25919705	619	0	0
wakeup_en_rd_A	25919705	1529	0	0
wakeup_en_regwen_rd_A	25919705	584	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25919705	15229	0	0
T11	15207	0	0	0
T14	428323	3	0	0
T15	384305	87	0	0
T23	0	70	0	0
T36	58951	0	0	0
T37	3629	0	0	0
T38	22488	0	0	0
T42	1697	0	0	0
T47	0	56	0	0
T70	1497	0	0	0
T73	0	10	0	0
T79	1141	0	0	0
T80	4998	0	0	0
T83	0	3	0	0
T84	0	28	0	0
T128	0	99	0	0
T129	0	14	0	0
T130	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25919705	41013	0	0
T11	15207	0	0	0
T14	428323	2796	0	0
T15	384305	0	0	0
T36	58951	90	0	0
T37	3629	0	0	0
T38	22488	0	0	0
T39	0	149	0	0
T42	1697	0	0	0
T70	1497	7	0	0
T71	0	17	0	0
T72	0	34	0	0
T79	1141	0	0	0
T80	4998	0	0	0
T83	0	609	0	0
T131	0	4	0	0
T132	0	28	0	0
T133	0	47	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25919705	772	0	0
T16	1428	0	0	0
T77	0	4	0	0
T82	0	9	0	0
T87	2943	0	0	0
T88	2166	0	0	0
T89	3146	0	0	0
T90	1387	0	0	0
T91	7636	0	0	0
T92	52469	0	0	0
T93	17389	0	0	0
T130	293010	8	0	0
T134	0	1	0	0
T135	0	6	0	0
T136	0	8	0	0
T137	0	10	0	0
T138	0	15	0	0
T139	0	15	0	0
T140	0	16	0	0
T141	5258	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25919705	759	0	0
T16	1428	0	0	0
T30	0	5	0	0
T77	0	2	0	0
T82	0	13	0	0
T87	2943	0	0	0
T88	2166	0	0	0
T89	3146	0	0	0
T90	1387	0	0	0
T91	7636	0	0	0
T92	52469	0	0	0
T93	17389	0	0	0
T130	293010	4	0	0
T134	0	5	0	0
T136	0	4	0	0
T137	0	3	0	0
T138	0	27	0	0
T139	0	11	0	0
T140	0	4	0	0
T141	5258	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25919705	619	0	0
T16	1428	0	0	0
T30	0	2	0	0
T77	0	10	0	0
T82	0	9	0	0
T87	2943	0	0	0
T88	2166	0	0	0
T89	3146	0	0	0
T90	1387	0	0	0
T91	7636	0	0	0
T92	52469	0	0	0
T93	17389	0	0	0
T130	293010	9	0	0
T135	0	5	0	0
T136	0	6	0	0
T137	0	1	0	0
T138	0	16	0	0
T139	0	6	0	0
T140	0	7	0	0
T141	5258	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25919705	1529	0	0
T16	1428	0	0	0
T30	0	4	0	0
T77	0	11	0	0
T82	0	12	0	0
T87	2943	0	0	0
T88	2166	0	0	0
T89	3146	0	0	0
T90	1387	0	0	0
T91	7636	0	0	0
T92	52469	0	0	0
T93	17389	0	0	0
T130	293010	10	0	0
T135	0	6	0	0
T136	0	14	0	0
T137	0	9	0	0
T138	0	15	0	0
T139	0	16	0	0
T140	0	8	0	0
T141	5258	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25919705	584	0	0
T16	1428	0	0	0
T30	0	1	0	0
T77	0	5	0	0
T82	0	9	0	0
T87	2943	0	0	0
T88	2166	0	0	0
T89	3146	0	0	0
T90	1387	0	0	0
T91	7636	0	0	0
T92	52469	0	0	0
T93	17389	0	0	0
T130	293010	2	0	0
T135	0	4	0	0
T136	0	4	0	0
T137	0	9	0	0
T138	0	12	0	0
T139	0	5	0	0
T140	0	5	0	0
T141	5258	0	0	0