Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	25365534	53678	0	0
IoStatusRise_A	25365534	59696	0	0
MainStatusFall_A	25365534	53678	0	0
MainStatusRise_A	25365534	59697	0	0
UsbStatusFall_A	25365534	37166	0	0
UsbStatusRise_A	25365534	41728	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25365534	53678	0	0
T1	1069	2	0	0
T2	2456	2	0	0
T3	50609	89	0	0
T4	9062	9	0	0
T5	42226	134	0	0
T6	1908	1	0	0
T7	1348	0	0	0
T8	13423	14	0	0
T9	1534	0	0	0
T10	2073	4	0	0
T14	0	907	0	0
T19	0	5	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25365534	59696	0	0
T1	1069	3	0	0
T2	2456	3	0	0
T3	50609	90	0	0
T4	9062	10	0	0
T5	42226	148	0	0
T6	1908	2	0	0
T7	1348	6	0	0
T8	13423	15	0	0
T9	1534	3	0	0
T10	2073	5	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25365534	53678	0	0
T1	1069	2	0	0
T2	2456	2	0	0
T3	50609	89	0	0
T4	9062	9	0	0
T5	42226	134	0	0
T6	1908	1	0	0
T7	1348	0	0	0
T8	13423	14	0	0
T9	1534	0	0	0
T10	2073	4	0	0
T14	0	907	0	0
T19	0	5	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25365534	59697	0	0
T1	1069	3	0	0
T2	2456	3	0	0
T3	50609	90	0	0
T4	9062	10	0	0
T5	42226	148	0	0
T6	1908	2	0	0
T7	1348	6	0	0
T8	13423	15	0	0
T9	1534	3	0	0
T10	2073	5	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25365534	37166	0	0
T1	1069	2	0	0
T2	2456	2	0	0
T3	50609	53	0	0
T4	9062	4	0	0
T5	42226	105	0	0
T6	1908	1	0	0
T7	1348	0	0	0
T8	13423	5	0	0
T9	1534	0	0	0
T10	2073	4	0	0
T14	0	691	0	0
T19	0	5	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25365534	41728	0	0
T1	1069	3	0	0
T2	2456	3	0	0
T3	50609	53	0	0
T4	9062	5	0	0
T5	42226	115	0	0
T6	1908	2	0	0
T7	1348	6	0	0
T8	13423	5	0	0
T9	1534	3	0	0
T10	2073	5	0	0