Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	25366120	5897	0	0
EscTimeoutStoppedByClReset_A	25365534	3604065	0	0
EscTimeoutTriggersReset_A	4943788	313	0	0
RomAllowActiveState_A	25365534	59284	0	0
RomAllowCheckGoodState_A	25365534	59334	0	0
RomBlockActiveState_A	25365534	29366	0	0
RomBlockCheckGoodState_A	25365534	409208	0	0
RomIntgChkDisFalse_A	25365534	24697777	0	0
RomIntgChkDisTrue_A	25365534	148250	0	0
RstreqChkEsctimeout_A	25365534	4092	0	0
RstreqChkFsmterm_A	25365534	160	0	0
RstreqChkGlbesc_A	25365534	4092	0	0
RstreqChkMainpd_A	25365534	977432	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25366120	5897	0	0
T11	15208	94	0	0
T12	0	8	0	0
T13	0	27	0	0
T15	384305	0	0	0
T36	58951	0	0	0
T37	3629	0	0	0
T38	22489	0	0	0
T42	1697	0	0	0
T70	1498	0	0	0
T79	1142	0	0	0
T80	4999	0	0	0
T131	2379	0	0	0
T142	0	154	0	0
T143	0	20	0	0
T144	0	156	0	0
T145	0	94	0	0
T146	0	163	0	0
T147	0	4	0	0
T148	0	2	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25365534	3604065	0	0
T1	1069	14	0	0
T2	2456	12	0	0
T3	50609	11645	0	0
T4	9062	1727	0	0
T5	42226	7647	0	0
T6	1908	14	0	0
T7	1348	58	0	0
T8	13423	2895	0	0
T9	1534	29	0	0
T10	2073	36	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4943788	313	0	0
T11	340	3	0	0
T12	0	3	0	0
T13	0	2	0	0
T15	60472	0	0	0
T36	5905	0	0	0
T37	811	0	0	0
T38	8052	0	0	0
T42	525	0	0	0
T70	480	0	0	0
T79	265	0	0	0
T80	384	0	0	0
T131	216	0	0	0
T142	0	2	0	0
T143	0	2	0	0
T144	0	2	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	2	0	0
T149	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25365534	59284	0	0
T1	1069	3	0	0
T2	2456	3	0	0
T3	50609	90	0	0
T4	9062	10	0	0
T5	42226	148	0	0
T6	1908	2	0	0
T7	1348	6	0	0
T8	13423	15	0	0
T9	1534	3	0	0
T10	2073	5	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25365534	59334	0	0
T1	1069	3	0	0
T2	2456	3	0	0
T3	50609	90	0	0
T4	9062	10	0	0
T5	42226	148	0	0
T6	1908	2	0	0
T7	1348	6	0	0
T8	13423	15	0	0
T9	1534	3	0	0
T10	2073	5	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25365534	29366	0	0
T11	15207	0	0	0
T14	428323	0	0	0
T15	384305	0	0	0
T19	1584	183	0	0
T24	0	1361	0	0
T36	58951	0	0	0
T37	3629	0	0	0
T38	22488	22	0	0
T42	1697	0	0	0
T70	1497	0	0	0
T79	1141	0	0	0
T150	0	23	0	0
T151	0	594	0	0
T152	0	24	0	0
T153	0	737	0	0
T154	0	486	0	0
T155	0	1086	0	0
T156	0	88	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25365534	409208	0	0
T3	50609	4051	0	0
T4	9062	0	0	0
T5	42226	529	0	0
T6	1908	0	0	0
T7	1348	0	0	0
T8	13423	0	0	0
T9	1534	0	0	0
T10	2073	0	0	0
T14	428323	2843	0	0
T15	0	3714	0	0
T19	1584	98	0	0
T24	0	837	0	0
T36	0	4081	0	0
T38	0	1313	0	0
T39	0	4089	0	0
T40	0	505	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25365534	24697777	0	0
T1	1069	969	0	0
T2	2456	2387	0	0
T3	50609	48659	0	0
T4	9062	8996	0	0
T5	42226	41202	0	0
T6	1908	1816	0	0
T7	1348	928	0	0
T8	13423	13333	0	0
T9	1534	1311	0	0
T10	2073	1641	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25365534	148250	0	0
T3	50609	1880	0	0
T4	9062	0	0	0
T5	42226	0	0	0
T6	1908	0	0	0
T7	1348	0	0	0
T8	13423	0	0	0
T9	1534	0	0	0
T10	2073	0	0	0
T14	428323	0	0	0
T19	1584	189	0	0
T24	0	292	0	0
T93	0	10149	0	0
T150	0	171	0	0
T151	0	1077	0	0
T153	0	156	0	0
T157	0	759	0	0
T158	0	716	0	0
T159	0	18280	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25365534	4092	0	0
T5	42226	25	0	0
T6	1908	0	0	0
T7	1348	5	0	0
T8	13423	0	0	0
T9	1534	2	0	0
T10	2073	0	0	0
T11	15207	1	0	0
T12	0	1	0	0
T14	428323	64	0	0
T15	0	79	0	0
T19	1584	2	0	0
T36	58951	0	0	0
T37	0	5	0	0
T42	0	4	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25365534	160	0	0
T20	30135	40	0	0
T21	0	40	0	0
T22	0	20	0	0
T25	0	40	0	0
T26	0	20	0	0
T27	818	0	0	0
T28	3733	0	0	0
T29	15337	0	0	0
T30	207052	0	0	0
T31	2830	0	0	0
T32	6347	0	0	0
T33	22564	0	0	0
T34	7033	0	0	0
T35	2988	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25365534	4092	0	0
T5	42226	25	0	0
T6	1908	0	0	0
T7	1348	5	0	0
T8	13423	0	0	0
T9	1534	2	0	0
T10	2073	0	0	0
T11	15207	1	0	0
T12	0	1	0	0
T14	428323	64	0	0
T15	0	79	0	0
T19	1584	2	0	0
T36	58951	0	0	0
T37	0	5	0	0
T42	0	4	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25365534	977432	0	0
T3	50609	4407	0	0
T4	9062	0	0	0
T5	42226	2586	0	0
T6	1908	0	0	0
T7	1348	0	0	0
T8	13423	0	0	0
T9	1534	0	0	0
T10	2073	0	0	0
T14	428323	9127	0	0
T15	0	15498	0	0
T19	1584	104	0	0
T36	0	4906	0	0
T37	0	96	0	0
T38	0	1719	0	0
T39	0	6429	0	0
T40	0	841	0	0