Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	577908	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

221754

1

T1

29

T2

1

T3

46

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	422543	1			T1	182		T2	1		T3	153
values[0x0]	188375	1			T1	34		T3	41		T4	3864
values[0x1]	188744	1			T1	28		T3	41		T4	3863

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	457758	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

341904

1

T1

92

T2

1

T3

89

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3594	1			T4	26		T10	1		T78	1
valid_sources[0x01]	5632	1			T1	2		T4	53		T8	1
valid_sources[0x02]	2157	1			T4	68		T78	3		T43	1
valid_sources[0x03]	2816	1			T4	50		T6	1		T37	1
valid_sources[0x04]	4160	1			T3	3		T4	62		T78	3
valid_sources[0x05]	2919	1			T4	77		T21	1		T78	3
valid_sources[0x06]	2172	1			T1	2		T4	45		T21	1
valid_sources[0x07]	2433	1			T1	1		T4	47		T56	1
valid_sources[0x08]	2192	1			T1	2		T4	37		T6	1
valid_sources[0x09]	2278	1			T1	2		T4	60		T37	1
valid_sources[0x0a]	2358	1			T4	68		T21	1		T78	4
valid_sources[0x0b]	2642	1			T4	46		T8	1		T37	3
valid_sources[0x0c]	4194	1			T1	2		T4	53		T6	2
valid_sources[0x0d]	2426	1			T1	1		T4	64		T8	7
valid_sources[0x0e]	3098	1			T4	83		T10	6		T37	4
valid_sources[0x0f]	3540	1			T1	1		T4	53		T8	3
valid_sources[0x10]	2230	1			T4	51		T10	1		T37	2
valid_sources[0x11]	4056	1			T1	1		T4	62		T21	1
valid_sources[0x12]	2943	1			T3	5		T4	47		T8	1
valid_sources[0x13]	2830	1			T1	5		T4	43		T43	1
valid_sources[0x14]	2308	1			T3	1		T4	75		T8	3
valid_sources[0x15]	3231	1			T4	37		T21	1		T35	5
valid_sources[0x16]	2353	1			T3	4		T4	68		T21	1
valid_sources[0x17]	2476	1			T4	82		T8	1		T37	1
valid_sources[0x18]	4503	1			T4	72		T35	6		T36	7
valid_sources[0x19]	4446	1			T4	82		T21	1		T56	2
valid_sources[0x1a]	2552	1			T1	3		T3	10		T4	49
valid_sources[0x1b]	5904	1			T4	55		T10	2		T56	2
valid_sources[0x1c]	3072	1			T3	4		T4	57		T8	1
valid_sources[0x1d]	2632	1			T4	85		T8	1		T10	15
valid_sources[0x1e]	2371	1			T4	77		T21	1		T13	8
valid_sources[0x1f]	4313	1			T3	21		T4	70		T78	2
valid_sources[0x20]	4667	1			T4	61		T21	1		T37	1
valid_sources[0x21]	5299	1			T1	2		T3	1		T4	79
valid_sources[0x22]	2583	1			T1	13		T4	63		T21	1
valid_sources[0x23]	3533	1			T4	40		T8	3		T37	2
valid_sources[0x24]	2248	1			T1	5		T4	75		T37	1
valid_sources[0x25]	2798	1			T4	57		T8	2		T78	2
valid_sources[0x26]	2482	1			T4	44		T8	1		T21	1
valid_sources[0x27]	2540	1			T1	2		T4	52		T21	1
valid_sources[0x28]	2502	1			T4	54		T8	5		T21	2
valid_sources[0x29]	2546	1			T4	37		T10	2		T37	1
valid_sources[0x2a]	3432	1			T4	47		T37	5		T35	5
valid_sources[0x2b]	3304	1			T4	60		T6	7		T8	1
valid_sources[0x2c]	2332	1			T1	7		T4	72		T21	1
valid_sources[0x2d]	3833	1			T3	3		T4	61		T6	1
valid_sources[0x2e]	2152	1			T1	1		T3	1		T4	29
valid_sources[0x2f]	2543	1			T4	59		T78	1		T35	2
valid_sources[0x30]	6141	1			T4	40		T8	1		T21	1
valid_sources[0x31]	2292	1			T4	52		T8	1		T21	1
valid_sources[0x32]	4158	1			T1	9		T3	1		T4	64
valid_sources[0x33]	2492	1			T3	2		T4	57		T37	2
valid_sources[0x34]	2659	1			T1	2		T4	74		T8	2
valid_sources[0x35]	2438	1			T1	4		T4	48		T13	3
valid_sources[0x36]	3753	1			T4	34		T21	1		T37	4
valid_sources[0x37]	2484	1			T4	48		T6	6		T37	1
valid_sources[0x38]	2418	1			T4	34		T37	3		T43	1
valid_sources[0x39]	2363	1			T4	61		T21	2		T35	7
valid_sources[0x3a]	2556	1			T3	2		T4	43		T8	1
valid_sources[0x3b]	3224	1			T1	1		T3	1		T4	89
valid_sources[0x3c]	3203	1			T1	4		T4	63		T8	5
valid_sources[0x3d]	3976	1			T4	60		T35	5		T36	15
valid_sources[0x3e]	2366	1			T4	61		T37	1		T43	1
valid_sources[0x3f]	2430	1			T4	62		T8	1		T13	1
valid_sources[0x40]	3032	1			T1	2		T4	63		T8	2
valid_sources[0x41]	3147	1			T3	1		T4	41		T56	1
valid_sources[0x42]	2450	1			T4	62		T8	7		T13	1
valid_sources[0x43]	2285	1			T3	2		T4	33		T37	1
valid_sources[0x44]	2804	1			T1	1		T4	48		T8	2
valid_sources[0x45]	2285	1			T1	1		T3	1		T4	61
valid_sources[0x46]	7539	1			T1	4		T4	28		T37	2
valid_sources[0x47]	2703	1			T1	5		T4	50		T10	4
valid_sources[0x48]	3845	1			T1	2		T4	91		T21	1
valid_sources[0x49]	4102	1			T1	1		T4	40		T78	6
valid_sources[0x4a]	3314	1			T4	73		T8	1		T21	2
valid_sources[0x4b]	2292	1			T3	1		T4	65		T8	1
valid_sources[0x4c]	2276	1			T3	1		T4	79		T8	1
valid_sources[0x4d]	2295	1			T1	7		T4	61		T21	1
valid_sources[0x4e]	2345	1			T4	62		T37	1		T35	3
valid_sources[0x4f]	2120	1			T4	62		T78	3		T56	1
valid_sources[0x50]	3212	1			T1	2		T4	56		T37	1
valid_sources[0x51]	2380	1			T4	49		T10	2		T37	1
valid_sources[0x52]	3907	1			T1	1		T4	61		T8	1
valid_sources[0x53]	2238	1			T4	51		T21	1		T37	1
valid_sources[0x54]	2636	1			T4	62		T35	2		T36	1
valid_sources[0x55]	3218	1			T4	52		T35	4		T36	3
valid_sources[0x56]	2488	1			T3	1		T4	48		T21	2
valid_sources[0x57]	2460	1			T4	58		T37	1		T13	1
valid_sources[0x58]	2918	1			T4	65		T13	1		T35	2
valid_sources[0x59]	2517	1			T1	1		T4	74		T5	1
valid_sources[0x5a]	4130	1			T4	70		T8	1		T37	2
valid_sources[0x5b]	3181	1			T3	2		T4	62		T21	1
valid_sources[0x5c]	2408	1			T3	12		T4	64		T21	1
valid_sources[0x5d]	2429	1			T1	7		T3	15		T4	86
valid_sources[0x5e]	2541	1			T1	3		T4	67		T21	1
valid_sources[0x5f]	2356	1			T3	1		T4	48		T21	1
valid_sources[0x60]	2138	1			T4	66		T35	4		T36	2
valid_sources[0x61]	2470	1			T4	54		T37	2		T35	1
valid_sources[0x62]	2737	1			T4	72		T37	2		T56	1
valid_sources[0x63]	2633	1			T1	3		T4	52		T6	7
valid_sources[0x64]	2082	1			T4	68		T78	5		T43	1
valid_sources[0x65]	2252	1			T4	70		T6	3		T13	1
valid_sources[0x66]	2201	1			T1	1		T4	58		T8	3
valid_sources[0x67]	2408	1			T4	70		T6	2		T8	2
valid_sources[0x68]	3263	1			T1	1		T4	52		T21	1
valid_sources[0x69]	2941	1			T3	4		T4	66		T8	8
valid_sources[0x6a]	2625	1			T1	1		T3	3		T4	43
valid_sources[0x6b]	3110	1			T1	2		T4	46		T56	1
valid_sources[0x6c]	2735	1			T3	2		T4	58		T21	1
valid_sources[0x6d]	3864	1			T4	54		T21	1		T78	6
valid_sources[0x6e]	2381	1			T1	1		T3	2		T4	86
valid_sources[0x6f]	3178	1			T4	51		T78	2		T35	3
valid_sources[0x70]	11884	1			T4	55		T8	2		T35	3
valid_sources[0x71]	4166	1			T1	2		T4	69		T35	1
valid_sources[0x72]	2748	1			T4	62		T56	1		T35	6
valid_sources[0x73]	3774	1			T4	49		T21	1		T35	4
valid_sources[0x74]	2246	1			T1	4		T3	9		T4	57
valid_sources[0x75]	2269	1			T4	60		T7	77		T21	1
valid_sources[0x76]	3133	1			T4	52		T8	5		T35	2
valid_sources[0x77]	2873	1			T3	5		T4	67		T6	3
valid_sources[0x78]	2320	1			T3	1		T4	63		T8	7
valid_sources[0x79]	3536	1			T4	78		T8	1		T10	1
valid_sources[0x7a]	2322	1			T1	2		T4	48		T9	1
valid_sources[0x7b]	3245	1			T4	55		T8	2		T21	2
valid_sources[0x7c]	2369	1			T1	1		T4	39		T8	1
valid_sources[0x7d]	2693	1			T4	68		T13	1		T35	4
valid_sources[0x7e]	3381	1			T3	5		T4	61		T21	2
valid_sources[0x7f]	2523	1			T4	70		T37	4		T35	3
valid_sources[0x80]	2417	1			T4	62		T56	4		T35	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

114605

1

T1

14

T2

1

T3

27

values[0x0]

all_enables

biggest_size

69733

1

T1

10

T3

12

T4

1353

values[0x1]

all_enables

biggest_size

37416

1

T1

5

T3

7

T4

679