SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34817 | 1 | T22 | 295 | T35 | 397 | T36 | 290 | ||||
others[1] | 35202 | 1 | T22 | 304 | T35 | 392 | T23 | 1 | ||||
others[2] | 34905 | 1 | T22 | 312 | T35 | 386 | T36 | 296 | ||||
others[3] | 58385 | 1 | T22 | 486 | T35 | 673 | T36 | 503 | ||||
false | 21790 | 1 | T4 | 520 | T7 | 3 | T21 | 10 | ||||
true | 32461 | 1 | T1 | 1 | T2 | 7 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34803 | 1 | T22 | 298 | T35 | 400 | T36 | 286 | ||||
others[1] | 35166 | 1 | T7 | 1 | T22 | 294 | T35 | 441 | ||||
others[2] | 35159 | 1 | T22 | 315 | T35 | 390 | T36 | 279 | ||||
others[3] | 58469 | 1 | T22 | 476 | T35 | 649 | T36 | 509 | ||||
false | 13473 | 1 | T4 | 260 | T7 | 2 | T21 | 5 | ||||
true | 24222 | 1 | T1 | 1 | T2 | 7 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 705 | 1 | T1 | 4 | T3 | 4 | T4 | 16 | ||||
others[1] | 797 | 1 | T1 | 5 | T3 | 2 | T4 | 16 | ||||
others[2] | 754 | 1 | T1 | 6 | T3 | 3 | T4 | 7 | ||||
others[3] | 1281 | 1 | T1 | 13 | T3 | 2 | T4 | 26 | ||||
false | 15251 | 1 | T1 | 3 | T2 | 7 | T3 | 18 | ||||
true | 4642 | 1 | T1 | 1 | T3 | 5 | T4 | 144 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |