Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T10
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T44,T79

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	27373789	6887	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	27373789	282120	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	27373789	11316386	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	27373789	282132	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	27373789	6887	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	27373789	282120	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	27373789	11316386	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	27373789	282132	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	6887	0	0
T4	556642	154	0	0
T5	15141	0	0	0
T6	920	0	0	0
T7	5168	0	0	0
T8	5872	0	0	0
T9	2260	0	0	0
T10	2538	0	0	0
T21	6925	3	0	0
T22	0	27	0	0
T35	0	21	0	0
T36	0	19	0	0
T37	13249	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T78	2899	0	0	0
T79	0	26	0	0
T80	0	1	0	0
T81	0	20	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	282120	0	0
T4	556642	5441	0	0
T5	15141	0	0	0
T6	920	0	0	0
T7	5168	0	0	0
T8	5872	0	0	0
T9	2260	0	0	0
T10	2538	0	0	0
T21	6925	131	0	0
T22	0	574	0	0
T35	0	1222	0	0
T36	0	467	0	0
T37	13249	0	0	0
T43	0	13	0	0
T44	0	474	0	0
T78	2899	0	0	0
T79	0	603	0	0
T80	0	9	0	0
T81	0	421	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	11316386	0	0
T4	556642	231792	0	0
T5	15141	0	0	0
T6	920	583	0	0
T7	5168	0	0	0
T8	5872	0	0	0
T9	2260	0	0	0
T10	2538	252	0	0
T13	0	558	0	0
T21	6925	2778	0	0
T22	0	13365	0	0
T37	13249	5116	0	0
T43	0	1616	0	0
T56	0	1658	0	0
T78	2899	0	0	0
T82	0	5990	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	282132	0	0
T4	556642	5441	0	0
T5	15141	0	0	0
T6	920	0	0	0
T7	5168	0	0	0
T8	5872	0	0	0
T9	2260	0	0	0
T10	2538	0	0	0
T21	6925	131	0	0
T22	0	574	0	0
T35	0	1222	0	0
T36	0	467	0	0
T37	13249	0	0	0
T43	0	13	0	0
T44	0	474	0	0
T78	2899	0	0	0
T79	0	603	0	0
T80	0	9	0	0
T81	0	421	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	6887	0	0
T4	556642	154	0	0
T5	15141	0	0	0
T6	920	0	0	0
T7	5168	0	0	0
T8	5872	0	0	0
T9	2260	0	0	0
T10	2538	0	0	0
T21	6925	3	0	0
T22	0	27	0	0
T35	0	21	0	0
T36	0	19	0	0
T37	13249	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T78	2899	0	0	0
T79	0	26	0	0
T80	0	1	0	0
T81	0	20	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	282120	0	0
T4	556642	5441	0	0
T5	15141	0	0	0
T6	920	0	0	0
T7	5168	0	0	0
T8	5872	0	0	0
T9	2260	0	0	0
T10	2538	0	0	0
T21	6925	131	0	0
T22	0	574	0	0
T35	0	1222	0	0
T36	0	467	0	0
T37	13249	0	0	0
T43	0	13	0	0
T44	0	474	0	0
T78	2899	0	0	0
T79	0	603	0	0
T80	0	9	0	0
T81	0	421	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	11316386	0	0
T4	556642	231792	0	0
T5	15141	0	0	0
T6	920	583	0	0
T7	5168	0	0	0
T8	5872	0	0	0
T9	2260	0	0	0
T10	2538	252	0	0
T13	0	558	0	0
T21	6925	2778	0	0
T22	0	13365	0	0
T37	13249	5116	0	0
T43	0	1616	0	0
T56	0	1658	0	0
T78	2899	0	0	0
T82	0	5990	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	282132	0	0
T4	556642	5441	0	0
T5	15141	0	0	0
T6	920	0	0	0
T7	5168	0	0	0
T8	5872	0	0	0
T9	2260	0	0	0
T10	2538	0	0	0
T21	6925	131	0	0
T22	0	574	0	0
T35	0	1222	0	0
T36	0	467	0	0
T37	13249	0	0	0
T43	0	13	0	0
T44	0	474	0	0
T78	2899	0	0	0
T79	0	603	0	0
T80	0	9	0	0
T81	0	421	0	0