Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	27925893	14942	0	0
intr_enable_rd_A	27925893	52599	0	0
reset_en_rd_A	27925893	1323	0	0
reset_en_regwen_rd_A	27925893	1243	0	0
wake_info_capture_dis_rd_A	27925893	1254	0	0
wakeup_en_rd_A	27925893	1835	0	0
wakeup_en_regwen_rd_A	27925893	1137	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27925893	14942	0	0
T4	556642	15	0	0
T5	15141	0	0	0
T6	920	0	0	0
T7	5168	0	0	0
T8	5872	0	0	0
T9	2260	0	0	0
T10	2538	0	0	0
T19	0	2	0	0
T20	0	9	0	0
T21	6925	0	0	0
T37	13249	0	0	0
T52	0	138	0	0
T55	0	20	0	0
T71	0	32	0	0
T78	2899	0	0	0
T86	0	68	0	0
T139	0	10	0	0
T140	0	9	0	0
T141	0	110	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27925893	52599	0	0
T4	556642	3889	0	0
T5	15141	0	0	0
T6	920	0	0	0
T7	5168	0	0	0
T8	5872	55	0	0
T9	2260	0	0	0
T10	2538	0	0	0
T13	0	26	0	0
T21	6925	0	0	0
T22	0	95	0	0
T37	13249	0	0	0
T43	0	8	0	0
T78	2899	0	0	0
T82	0	57	0	0
T142	0	49	0	0
T143	0	50	0	0
T144	0	8	0	0
T145	0	1	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27925893	1323	0	0
T4	556642	28	0	0
T5	15141	0	0	0
T6	920	0	0	0
T7	5168	0	0	0
T8	5872	0	0	0
T9	2260	0	0	0
T10	2538	0	0	0
T19	0	2	0	0
T21	6925	0	0	0
T37	13249	0	0	0
T78	2899	0	0	0
T87	0	6	0	0
T88	0	4	0	0
T89	0	3	0	0
T146	0	3	0	0
T147	0	1	0	0
T148	0	4	0	0
T149	0	2	0	0
T150	0	8	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27925893	1243	0	0
T4	556642	14	0	0
T5	15141	0	0	0
T6	920	0	0	0
T7	5168	0	0	0
T8	5872	0	0	0
T9	2260	0	0	0
T10	2538	0	0	0
T21	6925	0	0	0
T37	13249	0	0	0
T71	0	2	0	0
T78	2899	0	0	0
T87	0	10	0	0
T88	0	8	0	0
T146	0	6	0	0
T147	0	13	0	0
T148	0	2	0	0
T149	0	5	0	0
T150	0	11	0	0
T151	0	5	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27925893	1254	0	0
T4	556642	31	0	0
T5	15141	0	0	0
T6	920	0	0	0
T7	5168	0	0	0
T8	5872	0	0	0
T9	2260	0	0	0
T10	2538	0	0	0
T21	6925	0	0	0
T37	13249	0	0	0
T71	0	5	0	0
T78	2899	0	0	0
T87	0	3	0	0
T89	0	1	0	0
T146	0	7	0	0
T147	0	4	0	0
T149	0	3	0	0
T150	0	5	0	0
T151	0	1	0	0
T152	0	7	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27925893	1835	0	0
T4	556642	19	0	0
T5	15141	0	0	0
T6	920	0	0	0
T7	5168	0	0	0
T8	5872	0	0	0
T9	2260	0	0	0
T10	2538	0	0	0
T21	6925	0	0	0
T37	13249	0	0	0
T71	0	8	0	0
T78	2899	0	0	0
T87	0	3	0	0
T88	0	2	0	0
T89	0	2	0	0
T146	0	8	0	0
T147	0	11	0	0
T149	0	3	0	0
T150	0	9	0	0
T152	0	3	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27925893	1137	0	0
T4	556642	19	0	0
T5	15141	0	0	0
T6	920	0	0	0
T7	5168	0	0	0
T8	5872	0	0	0
T9	2260	0	0	0
T10	2538	0	0	0
T21	6925	0	0	0
T37	13249	0	0	0
T71	0	1	0	0
T78	2899	0	0	0
T87	0	1	0	0
T146	0	5	0	0
T147	0	9	0	0
T148	0	6	0	0
T149	0	1	0	0
T150	0	5	0	0
T151	0	4	0	0
T152	0	5	0	0