Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	27373789	60536	0	0
IoStatusRise_A	27373789	67278	0	0
MainStatusFall_A	27373789	60536	0	0
MainStatusRise_A	27373789	67288	0	0
UsbStatusFall_A	27373789	42213	0	0
UsbStatusRise_A	27373789	47280	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	60536	0	0
T1	6346	1	0	0
T2	4543	0	0	0
T3	8489	31	0	0
T4	556642	1321	0	0
T5	15141	3	0	0
T6	920	4	0	0
T7	5168	8	0	0
T8	5872	25	0	0
T9	2260	0	0	0
T10	2538	6	0	0
T21	0	9	0	0
T37	0	14	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	67278	0	0
T1	6346	2	0	0
T2	4543	7	0	0
T3	8489	33	0	0
T4	556642	1454	0	0
T5	15141	4	0	0
T6	920	5	0	0
T7	5168	10	0	0
T8	5872	26	0	0
T9	2260	3	0	0
T10	2538	7	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	60536	0	0
T1	6346	1	0	0
T2	4543	0	0	0
T3	8489	31	0	0
T4	556642	1321	0	0
T5	15141	3	0	0
T6	920	4	0	0
T7	5168	8	0	0
T8	5872	25	0	0
T9	2260	0	0	0
T10	2538	6	0	0
T21	0	9	0	0
T37	0	14	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	67288	0	0
T1	6346	2	0	0
T2	4543	7	0	0
T3	8489	33	0	0
T4	556642	1454	0	0
T5	15141	4	0	0
T6	920	5	0	0
T7	5168	10	0	0
T8	5872	26	0	0
T9	2260	3	0	0
T10	2538	7	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	42213	0	0
T1	6346	1	0	0
T2	4543	0	0	0
T3	8489	31	0	0
T4	556642	935	0	0
T5	15141	3	0	0
T6	920	5	0	0
T7	5168	8	0	0
T8	5872	25	0	0
T9	2260	0	0	0
T10	2538	3	0	0
T21	0	5	0	0
T37	0	6	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	47280	0	0
T1	6346	2	0	0
T2	4543	7	0	0
T3	8489	33	0	0
T4	556642	1033	0	0
T5	15141	4	0	0
T6	920	5	0	0
T7	5168	10	0	0
T8	5872	26	0	0
T9	2260	3	0	0
T10	2538	3	0	0