Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	27374390	5234	0	0
EscTimeoutStoppedByClReset_A	27373789	3889072	0	0
EscTimeoutTriggersReset_A	5307298	311	0	0
RomAllowActiveState_A	27373789	66906	0	0
RomAllowCheckGoodState_A	27373789	66956	0	0
RomBlockActiveState_A	27373789	26016	0	0
RomBlockCheckGoodState_A	27373789	436855	0	0
RomIntgChkDisFalse_A	27373789	26666665	0	0
RomIntgChkDisTrue_A	27373789	136447	0	0
RstreqChkEsctimeout_A	27373789	5020	0	0
RstreqChkFsmterm_A	27373789	120	0	0
RstreqChkGlbesc_A	27373789	5020	0	0
RstreqChkMainpd_A	27373789	1108041	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27374390	5234	0	0
T5	15142	144	0	0
T6	920	0	0	0
T7	5168	0	0	0
T8	5872	0	0	0
T9	2261	0	0	0
T10	2539	0	0	0
T11	0	33	0	0
T12	0	2	0	0
T21	6925	0	0	0
T33	0	8	0	0
T34	2844	0	0	0
T37	13249	0	0	0
T38	0	44	0	0
T39	0	120	0	0
T78	2900	0	0	0
T96	0	9	0	0
T101	0	144	0	0
T153	0	31	0	0
T154	0	175	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	3889072	0	0
T1	6346	12	0	0
T2	4543	112	0	0
T3	8489	1474	0	0
T4	556642	70377	0	0
T5	15141	34	0	0
T6	920	29	0	0
T7	5168	310	0	0
T8	5872	656	0	0
T9	2260	44	0	0
T10	2538	439	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5307298	311	0	0
T5	352	3	0	0
T6	302	0	0	0
T7	403	0	0	0
T8	854	0	0	0
T9	221	0	0	0
T10	978	0	0	0
T11	0	3	0	0
T12	0	4	0	0
T21	754	0	0	0
T33	0	4	0	0
T34	919	0	0	0
T37	1531	0	0	0
T38	0	3	0	0
T39	0	3	0	0
T78	1471	0	0	0
T96	0	2	0	0
T101	0	3	0	0
T153	0	2	0	0
T155	0	6	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	66906	0	0
T1	6346	2	0	0
T2	4543	7	0	0
T3	8489	33	0	0
T4	556642	1453	0	0
T5	15141	4	0	0
T6	920	5	0	0
T7	5168	10	0	0
T8	5872	26	0	0
T9	2260	3	0	0
T10	2538	7	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	66956	0	0
T1	6346	2	0	0
T2	4543	7	0	0
T3	8489	33	0	0
T4	556642	1453	0	0
T5	15141	4	0	0
T6	920	5	0	0
T7	5168	10	0	0
T8	5872	26	0	0
T9	2260	3	0	0
T10	2538	7	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	26016	0	0
T7	5168	913	0	0
T8	5872	0	0	0
T9	2260	0	0	0
T10	2538	0	0	0
T11	2452	0	0	0
T21	6925	0	0	0
T22	0	15	0	0
T23	0	90	0	0
T34	2843	0	0	0
T36	0	6	0	0
T37	13249	0	0	0
T42	0	589	0	0
T56	2938	0	0	0
T78	2899	0	0	0
T81	0	24	0	0
T103	0	892	0	0
T106	0	30	0	0
T156	0	3	0	0
T157	0	47	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	436855	0	0
T4	556642	5964	0	0
T5	15141	0	0	0
T6	920	0	0	0
T7	5168	623	0	0
T8	5872	0	0	0
T9	2260	0	0	0
T10	2538	0	0	0
T21	6925	114	0	0
T22	0	1289	0	0
T35	0	4162	0	0
T36	0	1332	0	0
T37	13249	0	0	0
T78	2899	0	0	0
T79	0	1325	0	0
T81	0	1269	0	0
T144	0	46	0	0
T156	0	711	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	26666665	0	0
T1	6346	6250	0	0
T2	4543	4013	0	0
T3	8489	8332	0	0
T4	556642	546699	0	0
T5	15141	15053	0	0
T6	920	870	0	0
T7	5168	4465	0	0
T8	5872	5779	0	0
T9	2260	2022	0	0
T10	2538	2455	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	136447	0	0
T7	5168	554	0	0
T8	5872	0	0	0
T9	2260	0	0	0
T10	2538	0	0	0
T11	2452	0	0	0
T21	6925	0	0	0
T22	0	691	0	0
T23	0	324	0	0
T34	2843	0	0	0
T36	0	329	0	0
T37	13249	0	0	0
T42	0	185	0	0
T56	2938	0	0	0
T78	2899	0	0	0
T79	0	833	0	0
T103	0	92	0	0
T106	0	309	0	0
T156	0	214	0	0
T157	0	303	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	5020	0	0
T3	8489	11	0	0
T4	556642	139	0	0
T5	15141	1	0	0
T6	920	0	0	0
T7	5168	2	0	0
T8	5872	9	0	0
T9	2260	2	0	0
T10	2538	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T21	6925	0	0	0
T23	0	2	0	0
T34	0	8	0	0
T37	13249	0	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	120	0	0
T16	21703	20	0	0
T17	7305	20	0	0
T18	0	20	0	0
T24	0	40	0	0
T25	0	20	0	0
T26	3363	0	0	0
T27	1408	0	0	0
T28	3150	0	0	0
T29	12410	0	0	0
T30	1507	0	0	0
T31	52251	0	0	0
T32	16475	0	0	0
T33	1390	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	5020	0	0
T3	8489	11	0	0
T4	556642	139	0	0
T5	15141	1	0	0
T6	920	0	0	0
T7	5168	2	0	0
T8	5872	9	0	0
T9	2260	2	0	0
T10	2538	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T21	6925	0	0	0
T23	0	2	0	0
T34	0	8	0	0
T37	13249	0	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27373789	1108041	0	0
T2	4543	28	0	0
T3	8489	1618	0	0
T4	556642	20666	0	0
T5	15141	0	0	0
T6	920	0	0	0
T7	5168	868	0	0
T8	5872	567	0	0
T9	2260	0	0	0
T10	2538	0	0	0
T21	6925	354	0	0
T22	0	1839	0	0
T23	0	40	0	0
T34	0	211	0	0
T35	0	4802	0	0