Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	563902	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

220749

1

T1

48

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	416525	1			T1	104		T2	1		T3	1
values[0x0]	183928	1			T1	51		T4	73		T5	10
values[0x1]	184198	1			T1	59		T4	57		T5	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	447000	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

337651

1

T1

66

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4108	1			T6	8		T18	45		T19	8
valid_sources[0x01]	2497	1			T1	1		T4	3		T6	5
valid_sources[0x02]	3131	1			T6	4		T18	53		T19	30
valid_sources[0x03]	2917	1			T1	1		T4	2		T6	9
valid_sources[0x04]	2756	1			T1	2		T4	1		T6	10
valid_sources[0x05]	2871	1			T6	4		T9	1		T18	50
valid_sources[0x06]	2514	1			T4	3		T6	11		T18	34
valid_sources[0x07]	4551	1			T4	3		T5	2		T6	6
valid_sources[0x08]	2682	1			T1	3		T6	15		T18	51
valid_sources[0x09]	2484	1			T1	1		T6	7		T18	60
valid_sources[0x0a]	3280	1			T1	2		T6	3		T18	38
valid_sources[0x0b]	2497	1			T6	12		T18	35		T19	4
valid_sources[0x0c]	2721	1			T1	3		T6	12		T18	50
valid_sources[0x0d]	6098	1			T4	2		T5	1		T6	5
valid_sources[0x0e]	3442	1			T6	7		T18	42		T19	28
valid_sources[0x0f]	2609	1			T1	1		T4	2		T5	1
valid_sources[0x10]	2631	1			T4	1		T5	2		T6	9
valid_sources[0x11]	2597	1			T1	4		T5	3		T6	6
valid_sources[0x12]	2322	1			T6	8		T8	2		T18	63
valid_sources[0x13]	2328	1			T6	6		T18	46		T19	32
valid_sources[0x14]	2804	1			T6	4		T18	47		T19	14
valid_sources[0x15]	3705	1			T6	6		T18	43		T22	13
valid_sources[0x16]	2847	1			T4	2		T6	12		T8	1
valid_sources[0x17]	2348	1			T5	1		T6	5		T18	57
valid_sources[0x18]	2505	1			T5	2		T6	8		T18	46
valid_sources[0x19]	2665	1			T6	5		T18	41		T19	27
valid_sources[0x1a]	3739	1			T6	10		T18	46		T19	7
valid_sources[0x1b]	2905	1			T1	1		T6	2		T18	57
valid_sources[0x1c]	2764	1			T4	1		T5	1		T6	10
valid_sources[0x1d]	2938	1			T4	1		T6	4		T8	1
valid_sources[0x1e]	2865	1			T1	4		T4	1		T5	1
valid_sources[0x1f]	2557	1			T4	1		T6	9		T18	41
valid_sources[0x20]	2314	1			T4	1		T6	8		T18	51
valid_sources[0x21]	3365	1			T4	1		T6	4		T18	34
valid_sources[0x22]	2646	1			T5	1		T6	6		T18	53
valid_sources[0x23]	6540	1			T4	1		T5	1		T6	6
valid_sources[0x24]	2460	1			T4	1		T5	2		T6	8
valid_sources[0x25]	2996	1			T1	5		T4	2		T6	9
valid_sources[0x26]	8112	1			T6	6		T18	38		T19	18
valid_sources[0x27]	2327	1			T6	11		T18	41		T19	11
valid_sources[0x28]	4353	1			T1	2		T4	1		T6	8
valid_sources[0x29]	2610	1			T1	1		T4	2		T6	9
valid_sources[0x2a]	2659	1			T1	7		T5	1		T6	8
valid_sources[0x2b]	2283	1			T5	1		T6	7		T18	45
valid_sources[0x2c]	2866	1			T1	1		T4	1		T6	8
valid_sources[0x2d]	2616	1			T4	3		T6	5		T9	1
valid_sources[0x2e]	2300	1			T5	1		T6	8		T14	6
valid_sources[0x2f]	3195	1			T1	4		T4	1		T5	1
valid_sources[0x30]	4744	1			T6	4		T18	33		T19	32
valid_sources[0x31]	2524	1			T6	8		T18	62		T19	10
valid_sources[0x32]	2767	1			T1	4		T4	2		T5	2
valid_sources[0x33]	2970	1			T4	2		T6	7		T18	45
valid_sources[0x34]	4215	1			T6	7		T18	48		T19	30
valid_sources[0x35]	2456	1			T4	4		T6	14		T18	34
valid_sources[0x36]	2410	1			T1	1		T4	2		T6	5
valid_sources[0x37]	2342	1			T4	1		T6	11		T18	33
valid_sources[0x38]	3269	1			T1	1		T4	1		T5	3
valid_sources[0x39]	3980	1			T4	1		T6	11		T9	4
valid_sources[0x3a]	2528	1			T4	1		T6	3		T18	43
valid_sources[0x3b]	3778	1			T6	7		T18	52		T19	9
valid_sources[0x3c]	3390	1			T4	1		T6	3		T18	52
valid_sources[0x3d]	3304	1			T1	4		T5	1		T6	4
valid_sources[0x3e]	2535	1			T5	1		T6	12		T18	62
valid_sources[0x3f]	3156	1			T4	2		T6	13		T18	47
valid_sources[0x40]	3391	1			T6	2		T18	40		T19	27
valid_sources[0x41]	3098	1			T1	1		T5	3		T6	5
valid_sources[0x42]	2856	1			T6	3		T18	30		T19	24
valid_sources[0x43]	3362	1			T4	1		T5	1		T6	4
valid_sources[0x44]	2628	1			T6	8		T8	1		T18	40
valid_sources[0x45]	2962	1			T5	1		T6	2		T18	49
valid_sources[0x46]	6492	1			T6	6		T8	1		T18	49
valid_sources[0x47]	2435	1			T6	8		T18	50		T19	14
valid_sources[0x48]	2814	1			T1	5		T6	11		T8	1
valid_sources[0x49]	2635	1			T4	2		T6	8		T18	34
valid_sources[0x4a]	3317	1			T4	2		T6	4		T18	43
valid_sources[0x4b]	4644	1			T6	8		T8	1		T18	39
valid_sources[0x4c]	2247	1			T6	10		T18	47		T19	25
valid_sources[0x4d]	2401	1			T1	6		T4	1		T5	2
valid_sources[0x4e]	3374	1			T4	4		T6	6		T14	12
valid_sources[0x4f]	3417	1			T6	4		T18	58		T19	23
valid_sources[0x50]	2670	1			T4	1		T6	12		T18	51
valid_sources[0x51]	2564	1			T4	1		T6	2		T18	37
valid_sources[0x52]	2331	1			T5	1		T6	7		T18	35
valid_sources[0x53]	3364	1			T4	1		T6	2		T9	1
valid_sources[0x54]	3956	1			T6	6		T18	50		T19	11
valid_sources[0x55]	2282	1			T6	5		T10	1		T18	43
valid_sources[0x56]	2413	1			T1	1		T6	10		T18	42
valid_sources[0x57]	3464	1			T1	6		T4	1		T6	9
valid_sources[0x58]	2528	1			T5	1		T6	14		T8	2
valid_sources[0x59]	2567	1			T4	3		T6	6		T18	54
valid_sources[0x5a]	2619	1			T4	2		T6	3		T18	37
valid_sources[0x5b]	3043	1			T1	1		T6	7		T18	44
valid_sources[0x5c]	2221	1			T1	4		T4	2		T6	4
valid_sources[0x5d]	4268	1			T1	1		T4	1		T6	4
valid_sources[0x5e]	2480	1			T4	3		T6	10		T18	38
valid_sources[0x5f]	2269	1			T4	2		T5	2		T6	2
valid_sources[0x60]	2645	1			T6	6		T9	1		T18	51
valid_sources[0x61]	3655	1			T1	4		T6	11		T18	56
valid_sources[0x62]	4507	1			T1	1		T4	2		T6	11
valid_sources[0x63]	2469	1			T4	2		T6	9		T18	42
valid_sources[0x64]	2709	1			T4	1		T6	5		T18	53
valid_sources[0x65]	3404	1			T4	3		T6	6		T18	33
valid_sources[0x66]	4773	1			T4	1		T6	9		T18	41
valid_sources[0x67]	3483	1			T6	6		T18	42		T19	15
valid_sources[0x68]	2716	1			T1	1		T4	1		T6	15
valid_sources[0x69]	2567	1			T6	6		T18	38		T19	10
valid_sources[0x6a]	2702	1			T1	6		T4	2		T6	6
valid_sources[0x6b]	2526	1			T4	1		T6	12		T18	46
valid_sources[0x6c]	4393	1			T4	1		T6	11		T18	53
valid_sources[0x6d]	2422	1			T4	1		T6	8		T18	31
valid_sources[0x6e]	2343	1			T6	7		T18	54		T22	13
valid_sources[0x6f]	2480	1			T6	4		T18	61		T19	7
valid_sources[0x70]	2390	1			T6	7		T18	53		T19	65
valid_sources[0x71]	3332	1			T4	4		T5	2		T6	2
valid_sources[0x72]	3411	1			T1	6		T6	4		T18	48
valid_sources[0x73]	2722	1			T4	2		T6	5		T18	40
valid_sources[0x74]	5969	1			T1	6		T4	1		T6	4
valid_sources[0x75]	4097	1			T4	1		T6	6		T18	42
valid_sources[0x76]	3919	1			T6	7		T18	39		T19	1
valid_sources[0x77]	2480	1			T4	1		T5	1		T6	14
valid_sources[0x78]	2900	1			T4	3		T6	10		T18	44
valid_sources[0x79]	3181	1			T4	1		T6	7		T18	44
valid_sources[0x7a]	2617	1			T6	7		T18	42		T19	24
valid_sources[0x7b]	2699	1			T4	2		T5	1		T6	6
valid_sources[0x7c]	3107	1			T6	8		T18	36		T19	25
valid_sources[0x7d]	3672	1			T4	2		T6	4		T10	3
valid_sources[0x7e]	2546	1			T6	5		T7	16		T18	45
valid_sources[0x7f]	3071	1			T4	1		T6	5		T18	49
valid_sources[0x80]	2250	1			T1	1		T4	2		T6	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

115386

1

T1

21

T2

1

T3

1

values[0x0]

all_enables

biggest_size

68350

1

T1

17

T4

33

T5

3

values[0x1]

all_enables

biggest_size

37013

1

T1

10

T4

14

T5

2