SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34908 | 1 | T23 | 1 | T36 | 411 | T24 | 281 | ||||
others[1] | 35108 | 1 | T36 | 392 | T24 | 306 | T145 | 315 | ||||
others[2] | 34826 | 1 | T36 | 387 | T24 | 303 | T25 | 1 | ||||
others[3] | 58511 | 1 | T23 | 1 | T36 | 685 | T24 | 514 | ||||
false | 19800 | 1 | T6 | 48 | T9 | 2 | T18 | 298 | ||||
true | 30340 | 1 | T1 | 1 | T2 | 3 | T3 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35093 | 1 | T36 | 369 | T24 | 324 | T144 | 1 | ||||
others[1] | 34777 | 1 | T23 | 1 | T36 | 404 | T24 | 312 | ||||
others[2] | 35200 | 1 | T23 | 1 | T36 | 420 | T24 | 288 | ||||
others[3] | 58285 | 1 | T36 | 676 | T24 | 489 | T26 | 1 | ||||
false | 12499 | 1 | T6 | 24 | T9 | 1 | T18 | 149 | ||||
true | 23096 | 1 | T1 | 1 | T2 | 3 | T3 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 748 | 1 | T18 | 10 | T19 | 12 | T22 | 12 | ||||
others[1] | 762 | 1 | T18 | 15 | T19 | 6 | T22 | 5 | ||||
others[2] | 755 | 1 | T18 | 8 | T19 | 12 | T22 | 14 | ||||
others[3] | 1282 | 1 | T18 | 14 | T19 | 9 | T22 | 25 | ||||
false | 14997 | 1 | T1 | 1 | T2 | 3 | T3 | 6 | ||||
true | 4530 | 1 | T6 | 4 | T18 | 47 | T19 | 71 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |