Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T8,T18

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	26561763	6489	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	26561763	280040	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	26561763	10994583	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	26561763	280018	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	26561763	6489	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	26561763	280040	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	26561763	10994583	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	26561763	280018	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	6489	0	0
T6	84516	16	0	0
T7	6968	0	0	0
T8	1477	3	0	0
T9	1518	1	0	0
T10	20158	0	0	0
T11	15346	0	0	0
T14	2040	0	0	0
T18	249745	75	0	0
T19	81336	21	0	0
T22	0	83	0	0
T29	1180	0	0	0
T32	0	9	0	0
T33	0	57	0	0
T35	0	7	0	0
T37	0	2	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	280040	0	0
T6	84516	791	0	0
T7	6968	0	0	0
T8	1477	248	0	0
T9	1518	10	0	0
T10	20158	0	0	0
T11	15346	0	0	0
T14	2040	0	0	0
T18	249745	1556	0	0
T19	81336	744	0	0
T22	0	2680	0	0
T29	1180	0	0	0
T32	0	226	0	0
T33	0	1507	0	0
T35	0	660	0	0
T37	0	149	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	10994583	0	0
T1	7910	2109	0	0
T2	1082	0	0	0
T3	1805	0	0	0
T4	16950	5888	0	0
T5	1897	879	0	0
T6	84516	40310	0	0
T7	6968	1427	0	0
T8	1477	182	0	0
T9	1518	1176	0	0
T10	20158	0	0	0
T14	0	316	0	0
T18	0	114293	0	0
T29	0	885	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	280018	0	0
T6	84516	791	0	0
T7	6968	0	0	0
T8	1477	248	0	0
T9	1518	10	0	0
T10	20158	0	0	0
T11	15346	0	0	0
T14	2040	0	0	0
T18	249745	1556	0	0
T19	81336	742	0	0
T22	0	2677	0	0
T29	1180	0	0	0
T32	0	224	0	0
T33	0	1509	0	0
T35	0	660	0	0
T37	0	149	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	6489	0	0
T6	84516	16	0	0
T7	6968	0	0	0
T8	1477	3	0	0
T9	1518	1	0	0
T10	20158	0	0	0
T11	15346	0	0	0
T14	2040	0	0	0
T18	249745	75	0	0
T19	81336	21	0	0
T22	0	83	0	0
T29	1180	0	0	0
T32	0	9	0	0
T33	0	57	0	0
T35	0	7	0	0
T37	0	2	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	280040	0	0
T6	84516	791	0	0
T7	6968	0	0	0
T8	1477	248	0	0
T9	1518	10	0	0
T10	20158	0	0	0
T11	15346	0	0	0
T14	2040	0	0	0
T18	249745	1556	0	0
T19	81336	744	0	0
T22	0	2680	0	0
T29	1180	0	0	0
T32	0	226	0	0
T33	0	1507	0	0
T35	0	660	0	0
T37	0	149	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	10994583	0	0
T1	7910	2109	0	0
T2	1082	0	0	0
T3	1805	0	0	0
T4	16950	5888	0	0
T5	1897	879	0	0
T6	84516	40310	0	0
T7	6968	1427	0	0
T8	1477	182	0	0
T9	1518	1176	0	0
T10	20158	0	0	0
T14	0	316	0	0
T18	0	114293	0	0
T29	0	885	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	280018	0	0
T6	84516	791	0	0
T7	6968	0	0	0
T8	1477	248	0	0
T9	1518	10	0	0
T10	20158	0	0	0
T11	15346	0	0	0
T14	2040	0	0	0
T18	249745	1556	0	0
T19	81336	742	0	0
T22	0	2677	0	0
T29	1180	0	0	0
T32	0	224	0	0
T33	0	1509	0	0
T35	0	660	0	0
T37	0	149	0	0