Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	27125629	15482	0	0
intr_enable_rd_A	27125629	36930	0	0
reset_en_rd_A	27125629	1405	0	0
reset_en_regwen_rd_A	27125629	1145	0	0
wake_info_capture_dis_rd_A	27125629	1168	0	0
wakeup_en_rd_A	27125629	2541	0	0
wakeup_en_regwen_rd_A	27125629	1218	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27125629	15482	0	0
T11	15346	0	0	0
T15	1439	0	0	0
T18	249745	4	0	0
T19	81336	11	0	0
T22	375887	7	0	0
T29	1180	0	0	0
T30	1041	0	0	0
T31	2314	0	0	0
T32	9007	0	0	0
T33	239039	33	0	0
T42	0	59	0	0
T108	0	42	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	30	0	0
T112	0	70	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27125629	36930	0	0
T4	16950	63	0	0
T5	1897	0	0	0
T6	84516	0	0	0
T7	6968	0	0	0
T8	1477	0	0	0
T9	1518	3	0	0
T10	20158	0	0	0
T14	2040	10	0	0
T18	249745	0	0	0
T29	1180	0	0	0
T36	0	189	0	0
T53	0	30	0	0
T54	0	64	0	0
T78	0	63	0	0
T79	0	199	0	0
T113	0	65	0	0
T114	0	3	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27125629	1405	0	0
T44	0	54	0	0
T65	0	4	0	0
T73	0	15	0	0
T74	0	24	0	0
T76	0	13	0	0
T109	132383	1	0	0
T110	221760	0	0	0
T115	0	9	0	0
T116	0	7	0	0
T117	0	8	0	0
T118	0	3	0	0
T119	8430	0	0	0
T120	2615	0	0	0
T121	15030	0	0	0
T122	1563	0	0	0
T123	3405	0	0	0
T124	929	0	0	0
T125	2429	0	0	0
T126	2905	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27125629	1145	0	0
T44	0	43	0	0
T65	0	11	0	0
T73	0	22	0	0
T74	0	32	0	0
T76	0	16	0	0
T109	132383	8	0	0
T110	221760	0	0	0
T115	0	3	0	0
T116	0	8	0	0
T118	0	7	0	0
T119	8430	0	0	0
T120	2615	0	0	0
T121	15030	0	0	0
T122	1563	0	0	0
T123	3405	0	0	0
T124	929	0	0	0
T125	2429	0	0	0
T126	2905	0	0	0
T127	0	7	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27125629	1168	0	0
T65	0	11	0	0
T73	0	11	0	0
T74	0	11	0	0
T76	0	14	0	0
T109	132383	6	0	0
T110	221760	3	0	0
T115	0	10	0	0
T116	0	9	0	0
T117	0	12	0	0
T119	8430	0	0	0
T120	2615	0	0	0
T121	15030	0	0	0
T122	1563	0	0	0
T123	3405	0	0	0
T124	929	0	0	0
T125	2429	0	0	0
T126	2905	0	0	0
T128	0	3	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27125629	2541	0	0
T65	0	6	0	0
T73	0	11	0	0
T74	0	13	0	0
T75	0	2	0	0
T76	0	12	0	0
T109	132383	1	0	0
T110	221760	0	0	0
T115	0	17	0	0
T116	0	8	0	0
T117	0	6	0	0
T119	8430	0	0	0
T120	2615	0	0	0
T121	15030	0	0	0
T122	1563	0	0	0
T123	3405	0	0	0
T124	929	0	0	0
T125	2429	0	0	0
T126	2905	0	0	0
T127	0	6	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27125629	1218	0	0
T65	0	9	0	0
T73	0	14	0	0
T74	0	21	0	0
T76	0	17	0	0
T115	359634	12	0	0
T116	0	7	0	0
T117	0	3	0	0
T118	0	6	0	0
T127	0	6	0	0
T128	0	8	0	0
T129	6938	0	0	0
T130	27637	0	0	0
T131	4465	0	0	0
T132	33843	0	0	0
T133	885	0	0	0
T134	15565	0	0	0
T135	4514	0	0	0
T136	1648	0	0	0
T137	37440	0	0	0