Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	26561763	58630	0	0
IoStatusRise_A	26561763	65287	0	0
MainStatusFall_A	26561763	58630	0	0
MainStatusRise_A	26561763	65288	0	0
UsbStatusFall_A	26561763	40861	0	0
UsbStatusRise_A	26561763	45942	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	58630	0	0
T1	7910	16	0	0
T2	1082	0	0	0
T3	1805	0	0	0
T4	16950	18	0	0
T5	1897	3	0	0
T6	84516	135	0	0
T7	6968	7	0	0
T8	1477	4	0	0
T9	1518	2	0	0
T10	20158	30	0	0
T14	0	4	0	0
T18	0	940	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	65287	0	0
T1	7910	17	0	0
T2	1082	3	0	0
T3	1805	6	0	0
T4	16950	19	0	0
T5	1897	4	0	0
T6	84516	156	0	0
T7	6968	8	0	0
T8	1477	5	0	0
T9	1518	3	0	0
T10	20158	51	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	58630	0	0
T1	7910	16	0	0
T2	1082	0	0	0
T3	1805	0	0	0
T4	16950	18	0	0
T5	1897	3	0	0
T6	84516	135	0	0
T7	6968	7	0	0
T8	1477	4	0	0
T9	1518	2	0	0
T10	20158	30	0	0
T14	0	4	0	0
T18	0	940	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	65288	0	0
T1	7910	17	0	0
T2	1082	3	0	0
T3	1805	6	0	0
T4	16950	19	0	0
T5	1897	4	0	0
T6	84516	156	0	0
T7	6968	8	0	0
T8	1477	5	0	0
T9	1518	3	0	0
T10	20158	51	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	40861	0	0
T1	7910	8	0	0
T2	1082	0	0	0
T3	1805	0	0	0
T4	16950	11	0	0
T5	1897	2	0	0
T6	84516	100	0	0
T7	6968	5	0	0
T8	1477	4	0	0
T9	1518	1	0	0
T10	20158	30	0	0
T14	0	4	0	0
T18	0	671	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	45942	0	0
T1	7910	8	0	0
T2	1082	3	0	0
T3	1805	6	0	0
T4	16950	11	0	0
T5	1897	2	0	0
T6	84516	113	0	0
T7	6968	6	0	0
T8	1477	5	0	0
T9	1518	1	0	0
T10	20158	51	0	0