Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	26562354	5517	0	0
EscTimeoutStoppedByClReset_A	26561763	3791030	0	0
EscTimeoutTriggersReset_A	4995780	338	0	0
RomAllowActiveState_A	26561763	64907	0	0
RomAllowCheckGoodState_A	26561763	64957	0	0
RomBlockActiveState_A	26561763	32953	0	0
RomBlockCheckGoodState_A	26561763	430654	0	0
RomIntgChkDisFalse_A	26561763	25850839	0	0
RomIntgChkDisTrue_A	26561763	144824	0	0
RstreqChkEsctimeout_A	26561763	4920	0	0
RstreqChkFsmterm_A	26561763	140	0	0
RstreqChkGlbesc_A	26561763	4920	0	0
RstreqChkMainpd_A	26561763	1073412	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26562354	5517	0	0
T11	15347	69	0	0
T12	15059	52	0	0
T13	0	111	0	0
T15	1440	0	0	0
T22	375888	0	0	0
T30	1042	0	0	0
T31	2315	0	0	0
T32	9008	0	0	0
T33	239040	0	0	0
T34	17581	0	0	0
T37	1353	0	0	0
T121	0	55	0	0
T138	0	3	0	0
T139	0	33	0	0
T140	0	3	0	0
T141	0	183	0	0
T142	0	56	0	0
T143	0	41	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	3791030	0	0
T1	7910	1660	0	0
T2	1082	24	0	0
T3	1805	10	0	0
T4	16950	4416	0	0
T5	1897	0	0	0
T6	84516	11507	0	0
T7	6968	2011	0	0
T8	1477	92	0	0
T9	1518	19	0	0
T10	20158	4533	0	0
T14	0	4	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4995780	338	0	0
T11	337	2	0	0
T12	706	3	0	0
T13	0	3	0	0
T15	607	0	0	0
T22	86828	0	0	0
T30	512	0	0	0
T31	192	0	0	0
T32	3498	0	0	0
T33	87010	0	0	0
T34	3046	0	0	0
T37	478	0	0	0
T121	0	3	0	0
T124	0	4	0	0
T138	0	4	0	0
T139	0	3	0	0
T140	0	4	0	0
T141	0	2	0	0
T142	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	64907	0	0
T1	7910	17	0	0
T2	1082	3	0	0
T3	1805	6	0	0
T4	16950	19	0	0
T5	1897	4	0	0
T6	84516	156	0	0
T7	6968	8	0	0
T8	1477	5	0	0
T9	1518	3	0	0
T10	20158	51	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	64957	0	0
T1	7910	17	0	0
T2	1082	3	0	0
T3	1805	6	0	0
T4	16950	19	0	0
T5	1897	4	0	0
T6	84516	156	0	0
T7	6968	8	0	0
T8	1477	5	0	0
T9	1518	3	0	0
T10	20158	51	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	32953	0	0
T23	5444	1218	0	0
T25	0	1129	0	0
T26	0	235	0	0
T36	21954	4	0	0
T38	5572	0	0	0
T54	18825	0	0	0
T78	3397	0	0	0
T113	7505	0	0	0
T114	1302	0	0	0
T122	0	6	0	0
T139	2374	0	0	0
T144	0	213	0	0
T145	0	7	0	0
T146	0	15	0	0
T147	0	47	0	0
T148	0	912	0	0
T149	5023	0	0	0
T150	1827	0	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	430654	0	0
T6	84516	552	0	0
T7	6968	0	0	0
T8	1477	0	0	0
T9	1518	23	0	0
T10	20158	0	0	0
T11	15346	0	0	0
T14	2040	0	0	0
T18	249745	3419	0	0
T19	81336	938	0	0
T22	0	3328	0	0
T23	0	1015	0	0
T29	1180	0	0	0
T32	0	252	0	0
T33	0	1928	0	0
T35	0	229	0	0
T36	0	997	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	25850839	0	0
T1	7910	7812	0	0
T2	1082	874	0	0
T3	1805	1301	0	0
T4	16950	16875	0	0
T5	1897	1821	0	0
T6	84516	82961	0	0
T7	6968	6913	0	0
T8	1477	1166	0	0
T9	1518	1453	0	0
T10	20158	17187	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	144824	0	0
T23	5444	1586	0	0
T24	0	1762	0	0
T25	0	1536	0	0
T26	0	1137	0	0
T36	21954	0	0	0
T38	5572	0	0	0
T54	18825	0	0	0
T78	3397	0	0	0
T113	7505	0	0	0
T114	1302	0	0	0
T122	0	1002	0	0
T139	2374	0	0	0
T144	0	865	0	0
T145	0	332	0	0
T147	0	480	0	0
T148	0	152	0	0
T149	5023	0	0	0
T150	1827	0	0	0
T151	0	3433	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	4920	0	0
T2	1082	2	0	0
T3	1805	5	0	0
T4	16950	0	0	0
T5	1897	0	0	0
T6	84516	2	0	0
T7	6968	0	0	0
T8	1477	0	0	0
T9	1518	0	0	0
T10	20158	10	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	2040	0	0	0
T18	0	61	0	0
T19	0	68	0	0
T22	0	121	0	0
T33	0	141	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	140	0	0
T10	20158	20	0	0
T11	15346	0	0	0
T14	2040	0	0	0
T15	1439	0	0	0
T18	249745	0	0	0
T19	81336	0	0	0
T20	0	20	0	0
T21	0	40	0	0
T22	375887	0	0	0
T27	0	20	0	0
T28	0	40	0	0
T29	1180	0	0	0
T30	1041	0	0	0
T31	2314	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	4920	0	0
T2	1082	2	0	0
T3	1805	5	0	0
T4	16950	0	0	0
T5	1897	0	0	0
T6	84516	2	0	0
T7	6968	0	0	0
T8	1477	0	0	0
T9	1518	0	0	0
T10	20158	10	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	2040	0	0	0
T18	0	61	0	0
T19	0	68	0	0
T22	0	121	0	0
T33	0	141	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26561763	1073412	0	0
T6	84516	1455	0	0
T7	6968	0	0	0
T8	1477	0	0	0
T9	1518	0	0	0
T10	20158	0	0	0
T11	15346	0	0	0
T14	2040	0	0	0
T15	0	21	0	0
T18	249745	5539	0	0
T19	81336	3216	0	0
T22	0	11335	0	0
T29	1180	0	0	0
T30	0	11	0	0
T32	0	453	0	0
T33	0	6288	0	0
T34	0	783	0	0
T35	0	1466	0	0