Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	497454	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

192779

1

T2

61

T3

37

T4

30

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	361538	1			T1	1		T2	116		T3	182
values[0x0]	163595	1			T2	63		T3	31		T4	13
values[0x1]	165100	1			T2	73		T3	31		T4	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	394145	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

296088

1

T2

99

T3

87

T4

38

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2143	1			T2	1		T3	1		T14	8
valid_sources[0x01]	2411	1			T2	3		T6	1		T14	2
valid_sources[0x02]	3108	1			T2	2		T6	6		T37	3
valid_sources[0x03]	2127	1			T14	3		T39	2		T40	8
valid_sources[0x04]	2202	1			T2	1		T3	1		T6	6
valid_sources[0x05]	3346	1			T5	1		T6	2		T14	1
valid_sources[0x06]	3461	1			T2	1		T3	1		T5	3
valid_sources[0x07]	8815	1			T2	1		T3	1		T5	1
valid_sources[0x08]	2813	1			T2	2		T3	1		T5	2
valid_sources[0x09]	2118	1			T3	2		T37	1		T14	1
valid_sources[0x0a]	2120	1			T2	1		T3	2		T5	1
valid_sources[0x0b]	2828	1			T2	1		T5	1		T14	1
valid_sources[0x0c]	2945	1			T2	1		T3	2		T7	3
valid_sources[0x0d]	2756	1			T2	2		T5	10		T14	4
valid_sources[0x0e]	3154	1			T2	2		T3	3		T5	3
valid_sources[0x0f]	2390	1			T2	1		T14	2		T63	4
valid_sources[0x10]	3210	1			T14	2		T63	1		T40	6
valid_sources[0x11]	2568	1			T2	1		T5	4		T9	15
valid_sources[0x12]	3187	1			T2	2		T3	1		T9	137
valid_sources[0x13]	3254	1			T2	1		T5	2		T14	5
valid_sources[0x14]	3329	1			T10	8		T37	4		T14	3
valid_sources[0x15]	2185	1			T2	1		T3	2		T14	3
valid_sources[0x16]	2024	1			T2	1		T3	1		T6	9
valid_sources[0x17]	2043	1			T2	4		T3	1		T5	1
valid_sources[0x18]	2000	1			T2	3		T3	1		T14	2
valid_sources[0x19]	2430	1			T2	2		T14	9		T94	1
valid_sources[0x1a]	1987	1			T14	3		T93	1		T94	2
valid_sources[0x1b]	4066	1			T2	1		T6	8		T7	1
valid_sources[0x1c]	4019	1			T2	2		T3	2		T6	3
valid_sources[0x1d]	2145	1			T3	1		T37	1		T14	1
valid_sources[0x1e]	3074	1			T3	3		T7	1		T37	1
valid_sources[0x1f]	1986	1			T2	1		T5	1		T14	4
valid_sources[0x20]	2123	1			T3	2		T5	4		T10	2
valid_sources[0x21]	2188	1			T5	3		T10	13		T14	1
valid_sources[0x22]	1969	1			T3	2		T5	5		T6	4
valid_sources[0x23]	1995	1			T2	2		T14	1		T63	1
valid_sources[0x24]	2141	1			T2	1		T3	2		T14	2
valid_sources[0x25]	2009	1			T3	2		T6	6		T14	1
valid_sources[0x26]	2409	1			T2	4		T3	1		T7	1
valid_sources[0x27]	2344	1			T2	1		T3	3		T14	5
valid_sources[0x28]	2242	1			T2	2		T3	3		T63	10
valid_sources[0x29]	2306	1			T2	6		T5	4		T7	2
valid_sources[0x2a]	2186	1			T3	1		T5	2		T14	2
valid_sources[0x2b]	4329	1			T2	1		T3	1		T6	6
valid_sources[0x2c]	2100	1			T6	3		T14	1		T93	3
valid_sources[0x2d]	4344	1			T2	1		T5	2		T37	1
valid_sources[0x2e]	2182	1			T14	4		T15	2		T40	10
valid_sources[0x2f]	2310	1			T2	2		T7	2		T14	3
valid_sources[0x30]	2277	1			T3	1		T7	2		T14	2
valid_sources[0x31]	2300	1			T3	2		T5	3		T14	5
valid_sources[0x32]	2356	1			T2	1		T5	1		T14	5
valid_sources[0x33]	2817	1			T14	6		T63	4		T93	4
valid_sources[0x34]	2451	1			T2	2		T3	2		T7	3
valid_sources[0x35]	2082	1			T5	1		T14	3		T63	1
valid_sources[0x36]	2171	1			T2	2		T7	1		T37	1
valid_sources[0x37]	2352	1			T3	1		T7	1		T94	1
valid_sources[0x38]	3058	1			T2	1		T10	29		T37	1
valid_sources[0x39]	2657	1			T14	6		T93	1		T39	1
valid_sources[0x3a]	4008	1			T2	3		T3	3		T14	2
valid_sources[0x3b]	2712	1			T2	1		T5	9		T6	3
valid_sources[0x3c]	2295	1			T2	2		T3	1		T5	3
valid_sources[0x3d]	2177	1			T2	2		T3	1		T37	1
valid_sources[0x3e]	2474	1			T3	1		T5	2		T7	1
valid_sources[0x3f]	2457	1			T2	2		T5	2		T7	2
valid_sources[0x40]	2029	1			T8	1		T14	2		T26	1
valid_sources[0x41]	3355	1			T2	1		T14	3		T94	1
valid_sources[0x42]	2877	1			T2	1		T3	1		T5	1
valid_sources[0x43]	7015	1			T2	1		T3	2		T5	4
valid_sources[0x44]	2097	1			T5	2		T14	3		T94	1
valid_sources[0x45]	2500	1			T5	1		T6	3		T25	25
valid_sources[0x46]	3018	1			T2	2		T3	1		T5	3
valid_sources[0x47]	3048	1			T3	1		T5	2		T37	1
valid_sources[0x48]	2015	1			T2	2		T3	1		T14	2
valid_sources[0x49]	2102	1			T2	1		T3	1		T5	1
valid_sources[0x4a]	2834	1			T14	2		T94	1		T26	1
valid_sources[0x4b]	2115	1			T2	1		T3	1		T5	1
valid_sources[0x4c]	3228	1			T3	1		T14	2		T93	2
valid_sources[0x4d]	2551	1			T3	1		T6	6		T37	4
valid_sources[0x4e]	2276	1			T2	1		T3	3		T5	1
valid_sources[0x4f]	2198	1			T2	1		T3	2		T6	2
valid_sources[0x50]	2559	1			T2	2		T3	1		T5	1
valid_sources[0x51]	2258	1			T3	1		T6	2		T94	1
valid_sources[0x52]	2898	1			T2	3		T3	1		T14	1
valid_sources[0x53]	2091	1			T2	1		T3	1		T10	1
valid_sources[0x54]	2734	1			T3	1		T14	2		T26	1
valid_sources[0x55]	1964	1			T5	2		T9	26		T14	3
valid_sources[0x56]	2104	1			T7	2		T37	2		T14	3
valid_sources[0x57]	3477	1			T2	3		T5	2		T6	5
valid_sources[0x58]	2425	1			T2	2		T3	1		T37	3
valid_sources[0x59]	2412	1			T2	2		T3	1		T5	1
valid_sources[0x5a]	2963	1			T5	3		T14	2		T93	6
valid_sources[0x5b]	2035	1			T2	2		T3	1		T5	2
valid_sources[0x5c]	2412	1			T2	1		T3	2		T5	1
valid_sources[0x5d]	5617	1			T2	1		T6	13		T10	2
valid_sources[0x5e]	2119	1			T3	2		T5	1		T37	1
valid_sources[0x5f]	1976	1			T2	2		T10	21		T37	1
valid_sources[0x60]	4501	1			T2	1		T5	3		T14	1
valid_sources[0x61]	2461	1			T3	1		T5	1		T7	1
valid_sources[0x62]	3268	1			T2	1		T14	2		T94	1
valid_sources[0x63]	2816	1			T2	1		T3	2		T5	1
valid_sources[0x64]	2213	1			T2	2		T3	1		T14	3
valid_sources[0x65]	2255	1			T2	1		T3	1		T63	2
valid_sources[0x66]	2001	1			T2	1		T6	2		T14	3
valid_sources[0x67]	2328	1			T14	5		T94	3		T39	1
valid_sources[0x68]	3113	1			T3	1		T37	2		T14	2
valid_sources[0x69]	2882	1			T3	3		T5	2		T7	1
valid_sources[0x6a]	2219	1			T2	1		T5	3		T7	1
valid_sources[0x6b]	3913	1			T5	1		T9	16		T14	3
valid_sources[0x6c]	5407	1			T3	1		T5	2		T37	5
valid_sources[0x6d]	2115	1			T2	2		T3	1		T14	6
valid_sources[0x6e]	2258	1			T2	1		T3	1		T5	1
valid_sources[0x6f]	3226	1			T2	2		T3	1		T14	3
valid_sources[0x70]	2243	1			T2	1		T3	1		T5	1
valid_sources[0x71]	2012	1			T2	1		T3	3		T5	2
valid_sources[0x72]	4316	1			T2	2		T3	1		T38	864
valid_sources[0x73]	2471	1			T14	5		T63	2		T39	1
valid_sources[0x74]	3127	1			T6	5		T14	1		T93	6
valid_sources[0x75]	2516	1			T9	14		T14	3		T63	1
valid_sources[0x76]	2354	1			T2	3		T3	3		T10	11
valid_sources[0x77]	2578	1			T2	1		T3	1		T14	7
valid_sources[0x78]	2299	1			T14	3		T63	4		T93	2
valid_sources[0x79]	3327	1			T2	2		T3	2		T5	1
valid_sources[0x7a]	2071	1			T2	2		T3	2		T14	3
valid_sources[0x7b]	5352	1			T14	3		T63	2		T15	1
valid_sources[0x7c]	3469	1			T3	1		T7	3		T14	3
valid_sources[0x7d]	2135	1			T2	1		T3	4		T5	2
valid_sources[0x7e]	2034	1			T2	1		T14	4		T39	1
valid_sources[0x7f]	2135	1			T2	2		T14	3		T63	6
valid_sources[0x80]	3649	1			T2	2		T5	1		T9	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

97468

1

T2

23

T3

16

T4

25

values[0x0]

all_enables

biggest_size

61604

1

T2

26

T3

16

T4

4

values[0x1]

all_enables

biggest_size

33707

1

T2

12

T3

5

T4

1