SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34708 | 1 | T25 | 1 | T38 | 416 | T26 | 1 | ||||
others[1] | 34674 | 1 | T38 | 420 | T27 | 297 | T33 | 284 | ||||
others[2] | 34936 | 1 | T38 | 376 | T26 | 1 | T27 | 318 | ||||
others[3] | 57811 | 1 | T38 | 677 | T27 | 485 | T33 | 501 | ||||
false | 18511 | 1 | T6 | 18 | T9 | 68 | T25 | 2 | ||||
true | 28286 | 1 | T1 | 3 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34690 | 1 | T38 | 424 | T26 | 1 | T27 | 304 | ||||
others[1] | 34820 | 1 | T38 | 399 | T27 | 322 | T33 | 313 | ||||
others[2] | 34697 | 1 | T38 | 396 | T27 | 302 | T33 | 303 | ||||
others[3] | 57829 | 1 | T38 | 636 | T27 | 481 | T33 | 502 | ||||
false | 11823 | 1 | T6 | 9 | T9 | 34 | T25 | 5 | ||||
true | 21650 | 1 | T1 | 3 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 652 | 1 | T3 | 5 | T5 | 3 | T9 | 2 | ||||
others[1] | 675 | 1 | T3 | 4 | T4 | 1 | T5 | 4 | ||||
others[2] | 700 | 1 | T3 | 5 | T5 | 10 | T9 | 1 | ||||
others[3] | 1098 | 1 | T3 | 9 | T5 | 8 | T9 | 1 | ||||
false | 13179 | 1 | T1 | 3 | T2 | 1 | T3 | 5 | ||||
true | 3909 | 1 | T3 | 1 | T4 | 7 | T5 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |