Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T9,T38

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	21959816	6035	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	21959816	228500	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	21959816	8949837	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	21959816	228513	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	21959816	6035	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	21959816	228500	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	21959816	8949837	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	21959816	228513	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	6035	0	0
T6	3957	6	0	0
T7	3010	0	0	0
T8	1171	0	0	0
T9	140217	12	0	0
T10	10196	0	0	0
T14	20212	4	0	0
T16	1665	0	0	0
T25	2857	0	0	0
T27	0	22	0	0
T32	0	3	0	0
T33	0	19	0	0
T34	0	23	0	0
T37	3277	0	0	0
T38	18533	22	0	0
T39	0	6	0	0
T40	0	16	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	228500	0	0
T6	3957	170	0	0
T7	3010	0	0	0
T8	1171	0	0	0
T9	140217	1203	0	0
T10	10196	0	0	0
T14	20212	336	0	0
T16	1665	0	0	0
T25	2857	0	0	0
T27	0	494	0	0
T32	0	664	0	0
T33	0	996	0	0
T34	0	1537	0	0
T37	3277	0	0	0
T38	18533	565	0	0
T39	0	225	0	0
T40	0	333	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	8949837	0	0
T2	19066	9187	0	0
T3	6198	0	0	0
T4	4561	0	0	0
T5	4352	0	0	0
T6	3957	2123	0	0
T7	3010	0	0	0
T8	1171	0	0	0
T9	140217	59319	0	0
T10	10196	5492	0	0
T14	0	5411	0	0
T15	0	2002	0	0
T16	1665	0	0	0
T38	0	8729	0	0
T39	0	7213	0	0
T63	0	2104	0	0
T64	0	12461	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	228513	0	0
T6	3957	170	0	0
T7	3010	0	0	0
T8	1171	0	0	0
T9	140217	1203	0	0
T10	10196	0	0	0
T14	20212	336	0	0
T16	1665	0	0	0
T25	2857	0	0	0
T27	0	494	0	0
T32	0	664	0	0
T33	0	996	0	0
T34	0	1537	0	0
T37	3277	0	0	0
T38	18533	565	0	0
T39	0	225	0	0
T40	0	333	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	6035	0	0
T6	3957	6	0	0
T7	3010	0	0	0
T8	1171	0	0	0
T9	140217	12	0	0
T10	10196	0	0	0
T14	20212	4	0	0
T16	1665	0	0	0
T25	2857	0	0	0
T27	0	22	0	0
T32	0	3	0	0
T33	0	19	0	0
T34	0	23	0	0
T37	3277	0	0	0
T38	18533	22	0	0
T39	0	6	0	0
T40	0	16	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	228500	0	0
T6	3957	170	0	0
T7	3010	0	0	0
T8	1171	0	0	0
T9	140217	1203	0	0
T10	10196	0	0	0
T14	20212	336	0	0
T16	1665	0	0	0
T25	2857	0	0	0
T27	0	494	0	0
T32	0	664	0	0
T33	0	996	0	0
T34	0	1537	0	0
T37	3277	0	0	0
T38	18533	565	0	0
T39	0	225	0	0
T40	0	333	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	8949837	0	0
T2	19066	9187	0	0
T3	6198	0	0	0
T4	4561	0	0	0
T5	4352	0	0	0
T6	3957	2123	0	0
T7	3010	0	0	0
T8	1171	0	0	0
T9	140217	59319	0	0
T10	10196	5492	0	0
T14	0	5411	0	0
T15	0	2002	0	0
T16	1665	0	0	0
T38	0	8729	0	0
T39	0	7213	0	0
T63	0	2104	0	0
T64	0	12461	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	228513	0	0
T6	3957	170	0	0
T7	3010	0	0	0
T8	1171	0	0	0
T9	140217	1203	0	0
T10	10196	0	0	0
T14	20212	336	0	0
T16	1665	0	0	0
T25	2857	0	0	0
T27	0	494	0	0
T32	0	664	0	0
T33	0	996	0	0
T34	0	1537	0	0
T37	3277	0	0	0
T38	18533	565	0	0
T39	0	225	0	0
T40	0	333	0	0