Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22519331	15092	0	0
intr_enable_rd_A	22519331	32565	0	0
reset_en_rd_A	22519331	1359	0	0
reset_en_regwen_rd_A	22519331	1140	0	0
wake_info_capture_dis_rd_A	22519331	1149	0	0
wakeup_en_rd_A	22519331	1517	0	0
wakeup_en_regwen_rd_A	22519331	1211	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22519331	15092	0	0
T12	810	0	0	0
T13	1351	0	0	0
T22	119270	12	0	0
T23	250915	17	0	0
T24	0	2	0	0
T67	0	10	0	0
T120	2720	0	0	0
T125	0	43	0	0
T126	0	29	0	0
T127	0	3	0	0
T128	0	14	0	0
T129	0	4	0	0
T130	0	21	0	0
T131	6988	0	0	0
T132	1223	0	0	0
T133	4395	0	0	0
T134	1123	0	0	0
T135	1737	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22519331	32565	0	0
T2	19066	35	0	0
T3	6198	0	0	0
T4	4561	0	0	0
T5	4352	110	0	0
T6	3957	0	0	0
T7	3010	0	0	0
T8	1171	0	0	0
T9	140217	0	0	0
T10	10196	0	0	0
T16	1665	0	0	0
T26	0	27	0	0
T33	0	153	0	0
T40	0	312	0	0
T132	0	1	0	0
T133	0	120	0	0
T136	0	125	0	0
T137	0	19	0	0
T138	0	29	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22519331	1359	0	0
T24	74760	5	0	0
T67	0	9	0	0
T82	0	3	0	0
T92	0	11	0	0
T122	21584	0	0	0
T123	15542	0	0	0
T127	0	9	0	0
T129	0	6	0	0
T139	0	10	0	0
T140	0	9	0	0
T141	0	5	0	0
T142	0	3	0	0
T143	3102	0	0	0
T144	2157	0	0	0
T145	13395	0	0	0
T146	11956	0	0	0
T147	51660	0	0	0
T148	1932	0	0	0
T149	855	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22519331	1140	0	0
T24	74760	6	0	0
T67	0	6	0	0
T82	0	2	0	0
T92	0	11	0	0
T122	21584	0	0	0
T123	15542	0	0	0
T127	0	3	0	0
T129	0	3	0	0
T139	0	10	0	0
T140	0	12	0	0
T141	0	9	0	0
T142	0	6	0	0
T143	3102	0	0	0
T144	2157	0	0	0
T145	13395	0	0	0
T146	11956	0	0	0
T147	51660	0	0	0
T148	1932	0	0	0
T149	855	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22519331	1149	0	0
T24	74760	5	0	0
T67	0	2	0	0
T82	0	1	0	0
T92	0	5	0	0
T122	21584	0	0	0
T123	15542	0	0	0
T127	0	2	0	0
T129	0	1	0	0
T139	0	15	0	0
T140	0	8	0	0
T141	0	6	0	0
T142	0	12	0	0
T143	3102	0	0	0
T144	2157	0	0	0
T145	13395	0	0	0
T146	11956	0	0	0
T147	51660	0	0	0
T148	1932	0	0	0
T149	855	0	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22519331	1517	0	0
T24	74760	2	0	0
T67	0	9	0	0
T82	0	2	0	0
T92	0	5	0	0
T122	21584	0	0	0
T123	15542	0	0	0
T127	0	1	0	0
T129	0	5	0	0
T139	0	10	0	0
T140	0	14	0	0
T141	0	11	0	0
T142	0	3	0	0
T143	3102	0	0	0
T144	2157	0	0	0
T145	13395	0	0	0
T146	11956	0	0	0
T147	51660	0	0	0
T148	1932	0	0	0
T149	855	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22519331	1211	0	0
T24	74760	12	0	0
T52	0	19	0	0
T82	0	3	0	0
T92	0	12	0	0
T114	0	25	0	0
T122	21584	0	0	0
T123	15542	0	0	0
T129	0	6	0	0
T139	0	17	0	0
T140	0	11	0	0
T142	0	15	0	0
T143	3102	0	0	0
T144	2157	0	0	0
T145	13395	0	0	0
T146	11956	0	0	0
T147	51660	0	0	0
T148	1932	0	0	0
T149	855	0	0	0
T150	0	12	0	0