Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	21959816	51938	0	0
IoStatusRise_A	21959816	57779	0	0
MainStatusFall_A	21959816	51938	0	0
MainStatusRise_A	21959816	57779	0	0
UsbStatusFall_A	21959816	36068	0	0
UsbStatusRise_A	21959816	40594	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	51938	0	0
T2	19066	20	0	0
T3	6198	1	0	0
T4	4561	18	0	0
T5	4352	1	0	0
T6	3957	17	0	0
T7	3010	8	0	0
T8	1171	0	0	0
T9	140217	190	0	0
T10	10196	17	0	0
T16	1665	0	0	0
T25	0	5	0	0
T37	0	13	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	57779	0	0
T1	2226	3	0	0
T2	19066	21	0	0
T3	6198	2	0	0
T4	4561	19	0	0
T5	4352	2	0	0
T6	3957	19	0	0
T7	3010	9	0	0
T8	1171	2	0	0
T9	140217	213	0	0
T10	10196	18	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	51938	0	0
T2	19066	20	0	0
T3	6198	1	0	0
T4	4561	18	0	0
T5	4352	1	0	0
T6	3957	17	0	0
T7	3010	8	0	0
T8	1171	0	0	0
T9	140217	190	0	0
T10	10196	17	0	0
T16	1665	0	0	0
T25	0	5	0	0
T37	0	13	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	57779	0	0
T1	2226	3	0	0
T2	19066	21	0	0
T3	6198	2	0	0
T4	4561	19	0	0
T5	4352	2	0	0
T6	3957	19	0	0
T7	3010	9	0	0
T8	1171	2	0	0
T9	140217	213	0	0
T10	10196	18	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	36068	0	0
T2	19066	14	0	0
T3	6198	1	0	0
T4	4561	18	0	0
T5	4352	1	0	0
T6	3957	12	0	0
T7	3010	8	0	0
T8	1171	0	0	0
T9	140217	129	0	0
T10	10196	9	0	0
T16	1665	0	0	0
T25	0	5	0	0
T37	0	13	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	40594	0	0
T1	2226	3	0	0
T2	19066	14	0	0
T3	6198	2	0	0
T4	4561	19	0	0
T5	4352	2	0	0
T6	3957	13	0	0
T7	3010	9	0	0
T8	1171	2	0	0
T9	140217	147	0	0
T10	10196	10	0	0