Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	21960426	6077	0	0
EscTimeoutStoppedByClReset_A	21959816	3027760	0	0
EscTimeoutTriggersReset_A	5070637	309	0	0
RomAllowActiveState_A	21959816	57378	0	0
RomAllowCheckGoodState_A	21959816	57428	0	0
RomBlockActiveState_A	21959816	30417	0	0
RomBlockCheckGoodState_A	21959816	398908	0	0
RomIntgChkDisFalse_A	21959816	21314962	0	0
RomIntgChkDisTrue_A	21959816	138983	0	0
RstreqChkEsctimeout_A	21959816	4279	0	0
RstreqChkFsmterm_A	21959816	180	0	0
RstreqChkGlbesc_A	21959816	4279	0	0
RstreqChkMainpd_A	21959816	860586	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21960426	6077	0	0
T11	15408	140	0	0
T36	1794	0	0	0
T43	2211	0	0	0
T65	5584	0	0	0
T66	12505	0	0	0
T73	0	52	0	0
T136	4607	0	0	0
T151	0	31	0	0
T152	0	56	0	0
T153	0	20	0	0
T154	0	12	0	0
T155	0	258	0	0
T156	0	56	0	0
T157	0	19	0	0
T158	0	145	0	0
T159	4391	0	0	0
T160	1844	0	0	0
T161	920	0	0	0
T162	1088	0	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	3027760	0	0
T1	2226	14	0	0
T2	19066	3721	0	0
T3	6198	13	0	0
T4	4561	466	0	0
T5	4352	12	0	0
T6	3957	608	0	0
T7	3010	193	0	0
T8	1171	0	0	0
T9	140217	25649	0	0
T10	10196	1523	0	0
T16	0	17	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5070637	309	0	0
T11	369	3	0	0
T12	0	5	0	0
T13	0	3	0	0
T36	558	0	0	0
T43	385	0	0	0
T65	2199	0	0	0
T66	1490	0	0	0
T73	0	2	0	0
T136	1362	0	0	0
T151	0	2	0	0
T152	0	3	0	0
T153	0	2	0	0
T154	0	2	0	0
T159	633	0	0	0
T160	1709	0	0	0
T161	304	0	0	0
T162	195	0	0	0
T163	0	3	0	0
T164	0	4	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	57378	0	0
T1	2226	3	0	0
T2	19066	21	0	0
T3	6198	2	0	0
T4	4561	12	0	0
T5	4352	2	0	0
T6	3957	19	0	0
T7	3010	9	0	0
T8	1171	2	0	0
T9	140217	213	0	0
T10	10196	18	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	57428	0	0
T1	2226	3	0	0
T2	19066	21	0	0
T3	6198	2	0	0
T4	4561	13	0	0
T5	4352	2	0	0
T6	3957	19	0	0
T7	3010	9	0	0
T8	1171	2	0	0
T9	140217	213	0	0
T10	10196	18	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	30417	0	0
T14	20212	0	0	0
T25	2857	605	0	0
T26	2492	292	0	0
T27	0	12	0	0
T37	3277	0	0	0
T38	18533	0	0	0
T39	9922	0	0	0
T63	3599	0	0	0
T64	18812	0	0	0
T79	0	192	0	0
T93	3535	0	0	0
T94	4927	0	0	0
T137	0	804	0	0
T165	0	624	0	0
T166	0	27	0	0
T167	0	1112	0	0
T168	0	1091	0	0
T169	0	6	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	398908	0	0
T6	3957	206	0	0
T7	3010	0	0	0
T8	1171	0	0	0
T9	140217	777	0	0
T10	10196	0	0	0
T14	20212	115	0	0
T16	1665	0	0	0
T25	2857	348	0	0
T26	0	115	0	0
T27	0	1306	0	0
T33	0	3895	0	0
T37	3277	0	0	0
T38	18533	1360	0	0
T39	0	207	0	0
T40	0	735	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	21314962	0	0
T1	2226	2038	0	0
T2	19066	18999	0	0
T3	6198	6132	0	0
T4	4561	3714	0	0
T5	4352	4271	0	0
T6	3957	3813	0	0
T7	3010	2949	0	0
T8	1171	1013	0	0
T9	140217	138507	0	0
T10	10196	10126	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	138983	0	0
T14	20212	0	0	0
T25	2857	1069	0	0
T26	2492	102	0	0
T27	0	489	0	0
T33	0	3394	0	0
T37	3277	0	0	0
T38	18533	0	0	0
T39	9922	0	0	0
T63	3599	0	0	0
T64	18812	0	0	0
T93	3535	0	0	0
T94	4927	0	0	0
T137	0	177	0	0
T145	0	131	0	0
T147	0	950	0	0
T165	0	361	0	0
T167	0	1566	0	0
T168	0	290	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	4279	0	0
T1	2226	2	0	0
T2	19066	0	0	0
T3	6198	0	0	0
T4	4561	6	0	0
T5	4352	0	0	0
T6	3957	0	0	0
T7	3010	4	0	0
T8	1171	1	0	0
T9	140217	12	0	0
T10	10196	0	0	0
T14	0	16	0	0
T25	0	2	0	0
T26	0	2	0	0
T37	0	7	0	0
T40	0	15	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	180	0	0
T11	15408	0	0	0
T19	27490	40	0	0
T20	0	20	0	0
T21	0	40	0	0
T27	21831	0	0	0
T28	0	40	0	0
T29	0	40	0	0
T30	10289	0	0	0
T31	5732	0	0	0
T32	3000	0	0	0
T33	56237	0	0	0
T34	57771	0	0	0
T35	1858	0	0	0
T36	1793	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	4279	0	0
T1	2226	2	0	0
T2	19066	0	0	0
T3	6198	0	0	0
T4	4561	6	0	0
T5	4352	0	0	0
T6	3957	0	0	0
T7	3010	4	0	0
T8	1171	1	0	0
T9	140217	12	0	0
T10	10196	0	0	0
T14	0	16	0	0
T25	0	2	0	0
T26	0	2	0	0
T37	0	7	0	0
T40	0	15	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21959816	860586	0	0
T4	4561	203	0	0
T5	4352	0	0	0
T6	3957	246	0	0
T7	3010	111	0	0
T8	1171	0	0	0
T9	140217	4180	0	0
T10	10196	0	0	0
T14	0	1616	0	0
T16	1665	16	0	0
T25	2857	91	0	0
T26	0	53	0	0
T37	3277	427	0	0
T38	0	1614	0	0