Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	465957	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

179682

1

T1

31

T3

69

T4

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	339491	1			T1	37		T2	1		T3	125
values[0x0]	152908	1			T1	16		T3	73		T4	11
values[0x1]	153240	1			T1	17		T3	69		T4	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	368773	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

276866

1

T1

34

T3

112

T4

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5646	1			T3	3		T4	1		T5	6
valid_sources[0x01]	2777	1			T8	1		T9	1		T26	1
valid_sources[0x02]	2880	1			T3	1		T6	2		T8	1
valid_sources[0x03]	2130	1			T3	3		T8	1		T29	2
valid_sources[0x04]	2274	1			T1	1		T3	1		T9	1
valid_sources[0x05]	2137	1			T3	1		T8	1		T10	3
valid_sources[0x06]	2559	1			T3	3		T8	1		T9	2
valid_sources[0x07]	2760	1			T26	8		T29	3		T27	2
valid_sources[0x08]	1963	1			T3	1		T26	4		T29	2
valid_sources[0x09]	1981	1			T8	2		T10	1		T29	1
valid_sources[0x0a]	1912	1			T3	2		T6	3		T8	3
valid_sources[0x0b]	1890	1			T8	2		T26	4		T13	7
valid_sources[0x0c]	1812	1			T8	1		T26	5		T29	1
valid_sources[0x0d]	1867	1			T4	1		T26	2		T13	8
valid_sources[0x0e]	1891	1			T5	2		T9	2		T26	2
valid_sources[0x0f]	1881	1			T3	2		T9	1		T26	2
valid_sources[0x10]	1981	1			T3	3		T4	2		T26	3
valid_sources[0x11]	3046	1			T8	3		T9	1		T10	5
valid_sources[0x12]	2013	1			T9	1		T10	4		T26	4
valid_sources[0x13]	2957	1			T3	2		T4	1		T26	1
valid_sources[0x14]	1985	1			T3	1		T6	1		T8	1
valid_sources[0x15]	2128	1			T3	1		T9	1		T26	2
valid_sources[0x16]	2471	1			T4	1		T5	7		T27	9
valid_sources[0x17]	2085	1			T1	1		T5	6		T8	4
valid_sources[0x18]	2242	1			T3	2		T9	2		T26	3
valid_sources[0x19]	1977	1			T8	1		T9	5		T26	6
valid_sources[0x1a]	2964	1			T3	2		T4	1		T9	3
valid_sources[0x1b]	1998	1			T3	2		T6	5		T9	1
valid_sources[0x1c]	2092	1			T1	4		T4	1		T26	5
valid_sources[0x1d]	3267	1			T5	1		T10	1		T26	1
valid_sources[0x1e]	2417	1			T3	1		T4	1		T5	5
valid_sources[0x1f]	2061	1			T3	1		T26	2		T29	2
valid_sources[0x20]	2481	1			T3	1		T8	1		T26	10
valid_sources[0x21]	2269	1			T10	1		T26	3		T27	4
valid_sources[0x22]	1971	1			T9	2		T26	2		T27	1
valid_sources[0x23]	2092	1			T1	1		T3	1		T5	5
valid_sources[0x24]	2977	1			T4	4		T5	4		T8	3
valid_sources[0x25]	2028	1			T1	3		T5	1		T8	2
valid_sources[0x26]	2159	1			T1	2		T9	1		T26	6
valid_sources[0x27]	2445	1			T3	1		T5	1		T6	1
valid_sources[0x28]	2139	1			T26	2		T27	2		T13	3
valid_sources[0x29]	1873	1			T26	2		T27	3		T13	5
valid_sources[0x2a]	2885	1			T5	2		T26	4		T27	1
valid_sources[0x2b]	3804	1			T26	3		T29	2		T27	2
valid_sources[0x2c]	3295	1			T9	2		T10	1		T26	1
valid_sources[0x2d]	2198	1			T3	3		T8	1		T9	1
valid_sources[0x2e]	2162	1			T3	2		T6	7		T7	1
valid_sources[0x2f]	2765	1			T5	5		T8	4		T26	2
valid_sources[0x30]	1943	1			T3	2		T5	2		T8	2
valid_sources[0x31]	2706	1			T26	2		T48	2		T27	5
valid_sources[0x32]	2427	1			T3	3		T8	1		T26	3
valid_sources[0x33]	1976	1			T9	1		T26	3		T27	1
valid_sources[0x34]	2815	1			T26	2		T27	5		T13	9
valid_sources[0x35]	1759	1			T5	5		T8	1		T26	5
valid_sources[0x36]	3053	1			T10	2		T26	3		T27	5
valid_sources[0x37]	2167	1			T8	3		T9	3		T10	18
valid_sources[0x38]	2168	1			T1	2		T3	1		T5	5
valid_sources[0x39]	2832	1			T3	1		T9	2		T26	3
valid_sources[0x3a]	1927	1			T3	2		T26	5		T27	5
valid_sources[0x3b]	2101	1			T1	1		T5	2		T9	1
valid_sources[0x3c]	3854	1			T3	2		T26	8		T29	2
valid_sources[0x3d]	2070	1			T1	4		T3	2		T26	2
valid_sources[0x3e]	2991	1			T3	2		T8	1		T26	3
valid_sources[0x3f]	2679	1			T3	1		T8	6		T10	4
valid_sources[0x40]	1893	1			T3	1		T8	1		T9	1
valid_sources[0x41]	1831	1			T1	3		T8	1		T9	1
valid_sources[0x42]	2164	1			T8	4		T9	1		T26	5
valid_sources[0x43]	1831	1			T3	3		T9	2		T26	4
valid_sources[0x44]	2670	1			T1	1		T3	3		T8	1
valid_sources[0x45]	2933	1			T3	2		T10	5		T26	7
valid_sources[0x46]	3285	1			T3	1		T5	4		T26	4
valid_sources[0x47]	2002	1			T8	1		T9	3		T26	5
valid_sources[0x48]	1953	1			T1	2		T3	1		T8	2
valid_sources[0x49]	2196	1			T3	2		T4	1		T26	4
valid_sources[0x4a]	4260	1			T3	2		T8	1		T9	1
valid_sources[0x4b]	1831	1			T3	3		T26	4		T29	1
valid_sources[0x4c]	1853	1			T3	1		T8	1		T9	2
valid_sources[0x4d]	2074	1			T3	1		T4	2		T8	1
valid_sources[0x4e]	2048	1			T2	1		T3	2		T8	2
valid_sources[0x4f]	2018	1			T3	2		T8	1		T26	6
valid_sources[0x50]	2253	1			T5	4		T8	2		T29	2
valid_sources[0x51]	2496	1			T3	1		T5	9		T26	1
valid_sources[0x52]	2372	1			T3	2		T8	4		T9	1
valid_sources[0x53]	1978	1			T3	1		T5	21		T26	5
valid_sources[0x54]	2077	1			T3	1		T10	6		T26	5
valid_sources[0x55]	1862	1			T4	1		T5	3		T8	1
valid_sources[0x56]	1957	1			T3	1		T26	4		T29	2
valid_sources[0x57]	2083	1			T3	2		T26	2		T27	1
valid_sources[0x58]	2188	1			T3	2		T8	2		T26	3
valid_sources[0x59]	1818	1			T1	1		T3	2		T8	1
valid_sources[0x5a]	2008	1			T5	6		T9	2		T26	3
valid_sources[0x5b]	2025	1			T8	2		T9	3		T26	3
valid_sources[0x5c]	2085	1			T3	3		T8	1		T10	3
valid_sources[0x5d]	1839	1			T3	2		T5	5		T9	1
valid_sources[0x5e]	1987	1			T3	1		T4	2		T8	1
valid_sources[0x5f]	2395	1			T3	1		T6	4		T26	2
valid_sources[0x60]	1970	1			T3	1		T5	2		T6	6
valid_sources[0x61]	1947	1			T3	1		T8	2		T9	1
valid_sources[0x62]	2913	1			T8	1		T9	1		T22	45
valid_sources[0x63]	1875	1			T8	1		T9	3		T26	2
valid_sources[0x64]	3327	1			T8	1		T9	2		T26	2
valid_sources[0x65]	1949	1			T5	1		T8	3		T10	5
valid_sources[0x66]	1980	1			T5	1		T9	2		T22	28
valid_sources[0x67]	1977	1			T1	1		T9	1		T26	2
valid_sources[0x68]	2365	1			T3	1		T8	1		T9	1
valid_sources[0x69]	1969	1			T26	3		T48	1		T27	2
valid_sources[0x6a]	2928	1			T3	5		T8	1		T26	3
valid_sources[0x6b]	2089	1			T3	1		T5	1		T8	1
valid_sources[0x6c]	3727	1			T3	1		T26	4		T29	2
valid_sources[0x6d]	1899	1			T1	2		T4	1		T9	1
valid_sources[0x6e]	2020	1			T3	1		T26	1		T29	2
valid_sources[0x6f]	2460	1			T26	3		T29	2		T48	1
valid_sources[0x70]	2256	1			T3	2		T8	1		T26	2
valid_sources[0x71]	2081	1			T3	5		T8	1		T26	2
valid_sources[0x72]	2805	1			T8	3		T10	1		T26	3
valid_sources[0x73]	2263	1			T4	1		T5	2		T9	1
valid_sources[0x74]	3673	1			T3	6		T8	1		T9	1
valid_sources[0x75]	1936	1			T3	3		T8	2		T9	1
valid_sources[0x76]	6062	1			T9	1		T26	4		T29	1
valid_sources[0x77]	2033	1			T3	2		T5	5		T8	3
valid_sources[0x78]	2268	1			T3	2		T4	2		T8	4
valid_sources[0x79]	4982	1			T1	2		T3	1		T5	1
valid_sources[0x7a]	2369	1			T3	3		T8	1		T9	2
valid_sources[0x7b]	2145	1			T9	2		T26	3		T27	1
valid_sources[0x7c]	2058	1			T3	2		T4	2		T8	2
valid_sources[0x7d]	3634	1			T3	4		T9	2		T26	5
valid_sources[0x7e]	2123	1			T5	2		T8	1		T9	6
valid_sources[0x7f]	2715	1			T3	1		T5	4		T8	1
valid_sources[0x80]	1962	1			T1	4		T8	2		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

91674

1

T1

20

T3

30

T4

6

values[0x0]

all_enables

biggest_size

57106

1

T1

7

T3

26

T4

3

values[0x1]

all_enables

biggest_size

30902

1

T1

4

T3

13

T4

1