SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34883 | 1 | T26 | 287 | T27 | 297 | T28 | 312 | ||||
others[1] | 35052 | 1 | T26 | 323 | T27 | 311 | T28 | 297 | ||||
others[2] | 34805 | 1 | T26 | 305 | T27 | 293 | T28 | 311 | ||||
others[3] | 58936 | 1 | T26 | 493 | T27 | 506 | T28 | 498 | ||||
false | 17182 | 1 | T8 | 26 | T26 | 50 | T29 | 34 | ||||
true | 26829 | 1 | T1 | 12 | T2 | 2 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34915 | 1 | T26 | 298 | T27 | 303 | T28 | 289 | ||||
others[1] | 35113 | 1 | T26 | 322 | T27 | 306 | T28 | 295 | ||||
others[2] | 34821 | 1 | T26 | 303 | T27 | 311 | T28 | 306 | ||||
others[3] | 58513 | 1 | T26 | 489 | T27 | 487 | T28 | 498 | ||||
false | 11190 | 1 | T8 | 13 | T26 | 50 | T29 | 17 | ||||
true | 20892 | 1 | T1 | 12 | T2 | 2 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 628 | 1 | T1 | 2 | T10 | 5 | T13 | 5 | ||||
others[1] | 700 | 1 | T1 | 3 | T5 | 2 | T10 | 5 | ||||
others[2] | 690 | 1 | T1 | 2 | T10 | 9 | T13 | 3 | ||||
others[3] | 1102 | 1 | T10 | 7 | T13 | 11 | T41 | 3 | ||||
false | 12873 | 1 | T1 | 21 | T2 | 2 | T3 | 1 | ||||
true | 3735 | 1 | T1 | 2 | T5 | 3 | T10 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |