Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T26,T48

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	21942880	5816	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	21942880	239926	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	21942880	8970990	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	21942880	239951	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	21942880	5816	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	21942880	239926	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	21942880	8970990	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	21942880	239951	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21942880	5816	0	0
T8	16623	10	0	0
T9	4150	0	0	0
T10	6905	0	0	0
T11	15137	0	0	0
T12	1520	0	0	0
T13	0	21	0	0
T16	1059	0	0	0
T22	2337	1	0	0
T26	56710	21	0	0
T27	0	25	0	0
T28	0	25	0	0
T29	9954	6	0	0
T48	3073	1	0	0
T81	0	1	0	0
T82	0	32	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21942880	239926	0	0
T8	16623	813	0	0
T9	4150	0	0	0
T10	6905	0	0	0
T11	15137	0	0	0
T12	1520	0	0	0
T13	0	578	0	0
T16	1059	0	0	0
T22	2337	13	0	0
T26	56710	1225	0	0
T27	0	577	0	0
T28	0	1191	0	0
T29	9954	211	0	0
T48	3073	200	0	0
T81	0	12	0	0
T82	0	906	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21942880	8970990	0	0
T3	10347	5630	0	0
T4	1552	906	0	0
T5	7339	0	0	0
T6	1383	223	0	0
T7	15542	0	0	0
T8	16623	10756	0	0
T9	4150	1819	0	0
T10	6905	0	0	0
T22	2337	1406	0	0
T26	56710	28668	0	0
T29	0	3702	0	0
T48	0	121	0	0
T81	0	1678	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21942880	239951	0	0
T8	16623	813	0	0
T9	4150	0	0	0
T10	6905	0	0	0
T11	15137	0	0	0
T12	1520	0	0	0
T13	0	578	0	0
T16	1059	0	0	0
T22	2337	13	0	0
T26	56710	1225	0	0
T27	0	577	0	0
T28	0	1191	0	0
T29	9954	211	0	0
T48	3073	200	0	0
T81	0	12	0	0
T82	0	906	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21942880	5816	0	0
T8	16623	10	0	0
T9	4150	0	0	0
T10	6905	0	0	0
T11	15137	0	0	0
T12	1520	0	0	0
T13	0	21	0	0
T16	1059	0	0	0
T22	2337	1	0	0
T26	56710	21	0	0
T27	0	25	0	0
T28	0	25	0	0
T29	9954	6	0	0
T48	3073	1	0	0
T81	0	1	0	0
T82	0	32	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21942880	239926	0	0
T8	16623	813	0	0
T9	4150	0	0	0
T10	6905	0	0	0
T11	15137	0	0	0
T12	1520	0	0	0
T13	0	578	0	0
T16	1059	0	0	0
T22	2337	13	0	0
T26	56710	1225	0	0
T27	0	577	0	0
T28	0	1191	0	0
T29	9954	211	0	0
T48	3073	200	0	0
T81	0	12	0	0
T82	0	906	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21942880	8970990	0	0
T3	10347	5630	0	0
T4	1552	906	0	0
T5	7339	0	0	0
T6	1383	223	0	0
T7	15542	0	0	0
T8	16623	10756	0	0
T9	4150	1819	0	0
T10	6905	0	0	0
T22	2337	1406	0	0
T26	56710	28668	0	0
T29	0	3702	0	0
T48	0	121	0	0
T81	0	1678	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21942880	239951	0	0
T8	16623	813	0	0
T9	4150	0	0	0
T10	6905	0	0	0
T11	15137	0	0	0
T12	1520	0	0	0
T13	0	578	0	0
T16	1059	0	0	0
T22	2337	13	0	0
T26	56710	1225	0	0
T27	0	577	0	0
T28	0	1191	0	0
T29	9954	211	0	0
T48	3073	200	0	0
T81	0	12	0	0
T82	0	906	0	0