Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	22503902	13005	0	0
intr_enable_rd_A	22503902	32119	0	0
reset_en_rd_A	22503902	1205	0	0
reset_en_regwen_rd_A	22503902	939	0	0
wake_info_capture_dis_rd_A	22503902	969	0	0
wakeup_en_rd_A	22503902	2295	0	0
wakeup_en_regwen_rd_A	22503902	880	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22503902	13005	0	0
T23	259865	4	0	0
T24	0	45	0	0
T25	0	3	0	0
T53	0	7	0	0
T54	0	77	0	0
T57	0	98	0	0
T125	2641	0	0	0
T130	0	9	0	0
T131	0	7	0	0
T132	0	5	0	0
T133	0	17	0	0
T134	6752	0	0	0
T135	2691	0	0	0
T136	2266	0	0	0
T137	49993	0	0	0
T138	23781	0	0	0
T139	4642	0	0	0
T140	4753	0	0	0
T141	1338	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22503902	32119	0	0
T4	1552	4	0	0
T5	7339	0	0	0
T6	1383	0	0	0
T7	15542	0	0	0
T8	16623	0	0	0
T9	4150	0	0	0
T10	6905	96	0	0
T14	0	277	0	0
T22	2337	0	0	0
T26	56710	169	0	0
T27	0	88	0	0
T29	9954	0	0	0
T65	0	53	0	0
T70	0	28	0	0
T81	0	11	0	0
T82	0	166	0	0
T83	0	81	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22503902	1205	0	0
T23	259865	5	0	0
T64	0	5	0	0
T98	0	11	0	0
T125	2641	0	0	0
T134	6752	0	0	0
T135	2691	0	0	0
T136	2266	0	0	0
T137	49993	0	0	0
T138	23781	0	0	0
T139	4642	0	0	0
T140	4753	0	0	0
T141	1338	0	0	0
T142	0	9	0	0
T143	0	6	0	0
T144	0	9	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	7	0	0
T148	0	9	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22503902	939	0	0
T64	0	18	0	0
T71	0	14	0	0
T86	0	26	0	0
T98	0	7	0	0
T104	33676	0	0	0
T142	114827	6	0	0
T143	0	3	0	0
T145	0	6	0	0
T146	0	12	0	0
T147	0	28	0	0
T148	0	9	0	0
T149	1854	0	0	0
T150	16980	0	0	0
T151	15455	0	0	0
T152	6148	0	0	0
T153	11973	0	0	0
T154	2433	0	0	0
T155	16163	0	0	0
T156	4842	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22503902	969	0	0
T23	259865	1	0	0
T64	0	3	0	0
T98	0	20	0	0
T125	2641	0	0	0
T134	6752	0	0	0
T135	2691	0	0	0
T136	2266	0	0	0
T137	49993	0	0	0
T138	23781	0	0	0
T139	4642	0	0	0
T140	4753	0	0	0
T141	1338	0	0	0
T142	0	8	0	0
T143	0	9	0	0
T145	0	12	0	0
T146	0	10	0	0
T147	0	17	0	0
T148	0	9	0	0
T157	0	1	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22503902	2295	0	0
T23	259865	1	0	0
T98	0	5	0	0
T125	2641	0	0	0
T134	6752	0	0	0
T135	2691	0	0	0
T136	2266	0	0	0
T137	49993	0	0	0
T138	23781	0	0	0
T139	4642	0	0	0
T140	4753	0	0	0
T141	1338	0	0	0
T142	0	8	0	0
T143	0	7	0	0
T144	0	4	0	0
T145	0	9	0	0
T146	0	7	0	0
T147	0	8	0	0
T148	0	18	0	0
T157	0	8	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22503902	880	0	0
T23	259865	9	0	0
T64	0	8	0	0
T98	0	11	0	0
T125	2641	0	0	0
T134	6752	0	0	0
T135	2691	0	0	0
T136	2266	0	0	0
T137	49993	0	0	0
T138	23781	0	0	0
T139	4642	0	0	0
T140	4753	0	0	0
T141	1338	0	0	0
T142	0	12	0	0
T144	0	3	0	0
T145	0	1	0	0
T146	0	4	0	0
T147	0	23	0	0
T148	0	4	0	0
T157	0	9	0	0