Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	21943442	5919	0	0
EscTimeoutStoppedByClReset_A	21942880	3010349	0	0
EscTimeoutTriggersReset_A	4520007	314	0	0
RomAllowActiveState_A	21942880	54125	0	0
RomAllowCheckGoodState_A	21942880	54175	0	0
RomBlockActiveState_A	21942880	30711	0	0
RomBlockCheckGoodState_A	21942880	387353	0	0
RomIntgChkDisFalse_A	21942880	21283328	0	0
RomIntgChkDisTrue_A	21942880	166067	0	0
RstreqChkEsctimeout_A	21942880	4157	0	0
RstreqChkFsmterm_A	21942880	200	0	0
RstreqChkGlbesc_A	21942880	4157	0	0
RstreqChkMainpd_A	21942880	894147	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21943442	5919	0	0
T2	2375	22	0	0
T3	10347	0	0	0
T4	1553	0	0	0
T5	7340	0	0	0
T6	1384	0	0	0
T7	15542	278	0	0
T8	16623	0	0	0
T9	4151	0	0	0
T10	6905	0	0	0
T11	0	55	0	0
T22	2337	0	0	0
T44	0	83	0	0
T136	0	28	0	0
T158	0	141	0	0
T159	0	142	0	0
T160	0	27	0	0
T161	0	139	0	0
T162	0	145	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21942880	3010349	0	0
T1	4458	446	0	0
T2	2375	12	0	0
T3	10347	1482	0	0
T4	1552	77	0	0
T5	7339	354	0	0
T6	1383	106	0	0
T7	15542	64	0	0
T8	16623	2279	0	0
T9	4150	591	0	0
T10	6905	11	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4520007	314	0	0
T2	208	2	0	0
T3	2091	0	0	0
T4	1985	0	0	0
T5	733	0	0	0
T6	1376	0	0	0
T7	202	3	0	0
T8	1559	0	0	0
T9	2473	0	0	0
T10	510	0	0	0
T11	0	3	0	0
T22	215	0	0	0
T43	0	6	0	0
T44	0	3	0	0
T158	0	3	0	0
T159	0	3	0	0
T160	0	3	0	0
T161	0	3	0	0
T163	0	4	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21942880	54125	0	0
T1	4458	12	0	0
T2	2375	3	0	0
T3	10347	21	0	0
T4	1552	4	0	0
T5	7339	12	0	0
T6	1383	4	0	0
T7	15542	5	0	0
T8	16623	28	0	0
T9	4150	18	0	0
T10	6905	2	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21942880	54175	0	0
T1	4458	13	0	0
T2	2375	3	0	0
T3	10347	21	0	0
T4	1552	4	0	0
T5	7339	13	0	0
T6	1383	4	0	0
T7	15542	5	0	0
T8	16623	28	0	0
T9	4150	18	0	0
T10	6905	2	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21942880	30711	0	0
T47	1179	144	0	0
T51	2854	583	0	0
T52	1481	60	0	0
T83	32492	0	0	0
T93	0	248	0	0
T102	0	325	0	0
T160	2546	0	0	0
T164	0	192	0	0
T165	0	1	0	0
T166	0	343	0	0
T167	0	460	0	0
T168	0	16	0	0
T169	1606	0	0	0
T170	1473	0	0	0
T171	18254	0	0	0
T172	3331	0	0	0
T173	2045	0	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21942880	387353	0	0
T8	16623	299	0	0
T9	4150	0	0	0
T10	6905	0	0	0
T11	15137	0	0	0
T12	1520	0	0	0
T13	0	988	0	0
T16	1059	0	0	0
T22	2337	0	0	0
T26	56710	4031	0	0
T27	0	1323	0	0
T28	0	2806	0	0
T29	9954	389	0	0
T48	3073	0	0	0
T51	0	287	0	0
T82	0	1396	0	0
T83	0	2228	0	0
T171	0	1387	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21942880	21283328	0	0
T1	4458	3565	0	0
T2	2375	2219	0	0
T3	10347	10280	0	0
T4	1552	1487	0	0
T5	7339	6392	0	0
T6	1383	1311	0	0
T7	15542	15490	0	0
T8	16623	16479	0	0
T9	4150	4081	0	0
T10	6905	6821	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21942880	166067	0	0
T11	15137	0	0	0
T12	1520	0	0	0
T13	54082	0	0	0
T16	1059	0	0	0
T26	56710	2671	0	0
T27	23489	509	0	0
T28	0	20818	0	0
T29	9954	0	0	0
T47	0	52	0	0
T48	3073	0	0	0
T52	0	25	0	0
T70	14342	0	0	0
T81	2585	0	0	0
T83	0	784	0	0
T93	0	71	0	0
T102	0	509	0	0
T164	0	906	0	0
T171	0	773	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21942880	4157	0	0
T1	4458	7	0	0
T2	2375	1	0	0
T3	10347	0	0	0
T4	1552	0	0	0
T5	7339	6	0	0
T6	1383	0	0	0
T7	15542	1	0	0
T8	16623	0	0	0
T9	4150	0	0	0
T10	6905	0	0	0
T11	0	1	0	0
T12	0	4	0	0
T13	0	36	0	0
T41	0	9	0	0
T43	0	1	0	0
T44	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21942880	200	0	0
T19	44281	40	0	0
T20	0	40	0	0
T21	0	40	0	0
T30	0	40	0	0
T31	0	40	0	0
T32	14172	0	0	0
T33	2983	0	0	0
T34	2215	0	0	0
T35	2264	0	0	0
T36	1689	0	0	0
T37	15296	0	0	0
T38	18155	0	0	0
T39	2433	0	0	0
T40	811	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21942880	4157	0	0
T1	4458	7	0	0
T2	2375	1	0	0
T3	10347	0	0	0
T4	1552	0	0	0
T5	7339	6	0	0
T6	1383	0	0	0
T7	15542	1	0	0
T8	16623	0	0	0
T9	4150	0	0	0
T10	6905	0	0	0
T11	0	1	0	0
T12	0	4	0	0
T13	0	36	0	0
T41	0	9	0	0
T43	0	1	0	0
T44	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21942880	894147	0	0
T1	4458	212	0	0
T2	2375	0	0	0
T3	10347	0	0	0
T4	1552	0	0	0
T5	7339	163	0	0
T6	1383	0	0	0
T7	15542	0	0	0
T8	16623	2092	0	0
T9	4150	0	0	0
T10	6905	0	0	0
T13	0	2507	0	0
T16	0	12	0	0
T26	0	4443	0	0
T27	0	1594	0	0
T29	0	819	0	0
T41	0	364	0	0
T42	0	92	0	0