Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	526184	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

207450

1

T1

1

T2

48

T3

28

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	387902	1			T1	1		T2	101		T3	182
values[0x0]	172240	1			T2	53		T3	32		T5	37
values[0x1]	173492	1			T2	59		T3	30		T5	25

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	416973	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

316661

1

T1

1

T2

77

T3

89

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2732	1			T2	1		T12	10		T14	3
valid_sources[0x01]	2428	1			T7	6		T39	1		T13	1
valid_sources[0x02]	2090	1			T12	4		T37	2		T38	2
valid_sources[0x03]	2444	1			T12	6		T39	1		T40	1
valid_sources[0x04]	4652	1			T8	2		T12	3		T38	8
valid_sources[0x05]	4110	1			T2	1		T7	4		T12	8
valid_sources[0x06]	2314	1			T2	2		T12	12		T14	1
valid_sources[0x07]	3167	1			T2	1		T12	11		T38	3
valid_sources[0x08]	5682	1			T2	1		T7	1		T12	5
valid_sources[0x09]	2162	1			T2	1		T12	6		T13	23
valid_sources[0x0a]	2353	1			T2	2		T12	3		T38	4
valid_sources[0x0b]	6121	1			T8	1		T12	3		T13	12
valid_sources[0x0c]	2142	1			T2	1		T12	5		T38	3
valid_sources[0x0d]	3279	1			T2	1		T12	5		T38	3
valid_sources[0x0e]	2665	1			T2	1		T12	3		T13	4
valid_sources[0x0f]	2619	1			T12	5		T13	13		T38	5
valid_sources[0x10]	3320	1			T10	1		T12	3		T13	834
valid_sources[0x11]	3318	1			T12	3		T14	6		T15	43
valid_sources[0x12]	3530	1			T12	5		T37	1		T38	3
valid_sources[0x13]	2864	1			T2	1		T12	5		T38	2
valid_sources[0x14]	2398	1			T2	1		T12	4		T38	6
valid_sources[0x15]	2484	1			T12	4		T39	1		T13	14
valid_sources[0x16]	2914	1			T7	4		T8	1		T12	7
valid_sources[0x17]	3265	1			T2	1		T7	10		T12	11
valid_sources[0x18]	2198	1			T8	1		T12	2		T39	1
valid_sources[0x19]	3011	1			T12	7		T37	1		T38	5
valid_sources[0x1a]	3632	1			T12	4		T13	25		T15	70
valid_sources[0x1b]	2222	1			T2	1		T12	4		T37	1
valid_sources[0x1c]	2391	1			T12	9		T39	1		T38	4
valid_sources[0x1d]	2463	1			T2	1		T12	7		T38	2
valid_sources[0x1e]	2728	1			T2	2		T12	7		T38	4
valid_sources[0x1f]	2114	1			T12	3		T39	2		T40	2
valid_sources[0x20]	3158	1			T2	1		T12	2		T38	10
valid_sources[0x21]	2667	1			T7	6		T12	5		T40	1
valid_sources[0x22]	2510	1			T12	7		T38	2		T15	55
valid_sources[0x23]	2864	1			T2	1		T12	16		T39	1
valid_sources[0x24]	2391	1			T12	8		T37	1		T38	3
valid_sources[0x25]	6658	1			T2	3		T8	2		T12	5
valid_sources[0x26]	2558	1			T2	1		T12	14		T38	1
valid_sources[0x27]	2451	1			T8	1		T12	8		T39	1
valid_sources[0x28]	2308	1			T2	1		T12	4		T38	2
valid_sources[0x29]	3338	1			T2	2		T12	7		T13	14
valid_sources[0x2a]	2283	1			T12	1		T39	1		T40	1
valid_sources[0x2b]	4118	1			T2	4		T12	4		T38	1
valid_sources[0x2c]	2255	1			T7	8		T12	13		T37	1
valid_sources[0x2d]	2253	1			T2	1		T12	6		T39	1
valid_sources[0x2e]	3431	1			T12	12		T14	2		T37	1
valid_sources[0x2f]	3943	1			T2	1		T7	3		T8	2
valid_sources[0x30]	2809	1			T2	1		T12	6		T39	1
valid_sources[0x31]	2145	1			T2	1		T12	5		T38	7
valid_sources[0x32]	2819	1			T2	2		T8	2		T12	9
valid_sources[0x33]	4676	1			T7	4		T8	1		T12	5
valid_sources[0x34]	2214	1			T12	4		T38	2		T15	29
valid_sources[0x35]	3571	1			T2	2		T12	6		T38	4
valid_sources[0x36]	2237	1			T12	5		T38	1		T15	86
valid_sources[0x37]	2270	1			T2	1		T12	5		T38	1
valid_sources[0x38]	3131	1			T2	1		T12	10		T38	1
valid_sources[0x39]	2476	1			T2	2		T12	11		T39	1
valid_sources[0x3a]	2525	1			T2	1		T12	6		T37	2
valid_sources[0x3b]	2216	1			T2	1		T8	1		T12	4
valid_sources[0x3c]	5591	1			T2	1		T8	4		T12	6
valid_sources[0x3d]	2241	1			T12	9		T13	15		T41	12
valid_sources[0x3e]	2283	1			T2	1		T12	3		T40	1
valid_sources[0x3f]	2273	1			T2	2		T12	6		T39	1
valid_sources[0x40]	2178	1			T2	2		T12	4		T38	4
valid_sources[0x41]	2255	1			T2	1		T39	1		T13	8
valid_sources[0x42]	2542	1			T2	1		T8	4		T12	4
valid_sources[0x43]	2926	1			T5	244		T12	9		T38	1
valid_sources[0x44]	3238	1			T12	7		T37	1		T38	5
valid_sources[0x45]	2175	1			T2	1		T12	6		T37	1
valid_sources[0x46]	2344	1			T12	4		T38	9		T15	38
valid_sources[0x47]	2179	1			T12	6		T13	15		T15	49
valid_sources[0x48]	2138	1			T12	5		T38	4		T15	39
valid_sources[0x49]	2822	1			T2	2		T12	7		T38	2
valid_sources[0x4a]	2424	1			T2	2		T12	2		T15	60
valid_sources[0x4b]	3110	1			T2	2		T39	1		T38	5
valid_sources[0x4c]	2378	1			T2	1		T7	3		T12	1
valid_sources[0x4d]	3912	1			T12	3		T13	14		T14	1
valid_sources[0x4e]	2496	1			T2	1		T7	6		T12	8
valid_sources[0x4f]	2727	1			T2	1		T12	5		T13	27
valid_sources[0x50]	2414	1			T12	4		T39	1		T38	4
valid_sources[0x51]	2131	1			T7	2		T39	1		T38	5
valid_sources[0x52]	3719	1			T2	1		T7	4		T12	2
valid_sources[0x53]	3083	1			T12	4		T14	6		T38	2
valid_sources[0x54]	2412	1			T7	15		T12	8		T38	5
valid_sources[0x55]	2207	1			T2	1		T12	1		T38	4
valid_sources[0x56]	3612	1			T2	2		T12	3		T40	1
valid_sources[0x57]	4107	1			T12	4		T38	5		T15	37
valid_sources[0x58]	2205	1			T2	2		T12	6		T38	5
valid_sources[0x59]	3670	1			T8	2		T12	5		T38	10
valid_sources[0x5a]	2152	1			T12	3		T15	61		T22	1
valid_sources[0x5b]	2330	1			T2	2		T12	3		T41	10
valid_sources[0x5c]	2322	1			T2	2		T12	5		T13	13
valid_sources[0x5d]	2892	1			T8	1		T12	6		T41	9
valid_sources[0x5e]	2326	1			T7	14		T8	2		T12	2
valid_sources[0x5f]	3393	1			T8	2		T12	5		T13	15
valid_sources[0x60]	1962	1			T2	1		T8	1		T40	1
valid_sources[0x61]	2431	1			T2	5		T12	10		T40	2
valid_sources[0x62]	2182	1			T2	1		T12	1		T38	4
valid_sources[0x63]	2238	1			T15	35		T74	1		T172	6
valid_sources[0x64]	2829	1			T2	1		T12	8		T39	1
valid_sources[0x65]	2959	1			T2	1		T12	3		T38	7
valid_sources[0x66]	2637	1			T4	1		T12	10		T13	3
valid_sources[0x67]	3870	1			T2	1		T12	2		T38	11
valid_sources[0x68]	3469	1			T12	8		T38	14		T15	46
valid_sources[0x69]	2770	1			T12	9		T40	1		T38	6
valid_sources[0x6a]	2237	1			T2	1		T12	1		T39	1
valid_sources[0x6b]	2395	1			T2	1		T7	5		T12	5
valid_sources[0x6c]	2305	1			T2	3		T12	2		T38	9
valid_sources[0x6d]	2692	1			T12	8		T39	1		T37	1
valid_sources[0x6e]	2376	1			T12	4		T13	7		T38	3
valid_sources[0x6f]	3221	1			T2	1		T12	3		T38	3
valid_sources[0x70]	7443	1			T8	1		T12	6		T38	8
valid_sources[0x71]	3826	1			T2	1		T12	6		T38	5
valid_sources[0x72]	3133	1			T2	2		T12	5		T39	2
valid_sources[0x73]	3648	1			T7	1		T12	12		T13	27
valid_sources[0x74]	2391	1			T2	2		T12	7		T38	2
valid_sources[0x75]	2707	1			T2	2		T8	1		T12	3
valid_sources[0x76]	2166	1			T7	7		T12	8		T38	1
valid_sources[0x77]	2421	1			T2	1		T12	5		T38	4
valid_sources[0x78]	3306	1			T12	9		T38	6		T15	60
valid_sources[0x79]	3732	1			T12	3		T13	13		T38	10
valid_sources[0x7a]	2942	1			T2	1		T12	3		T41	6
valid_sources[0x7b]	3187	1			T2	1		T12	11		T15	44
valid_sources[0x7c]	2495	1			T2	1		T12	6		T13	28
valid_sources[0x7d]	2870	1			T2	1		T12	3		T39	1
valid_sources[0x7e]	2916	1			T2	1		T8	1		T12	9
valid_sources[0x7f]	3101	1			T2	2		T12	5		T39	1
valid_sources[0x80]	2540	1			T2	1		T12	2		T39	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

107265

1

T1

1

T2

20

T3

17

values[0x0]

all_enables

biggest_size

64521

1

T2

17

T3

8

T5

12

values[0x1]

all_enables

biggest_size

35664

1

T2

11

T3

3

T5

4