SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34867 | 1 | T23 | 394 | T35 | 374 | T36 | 390 | ||||
others[1] | 35006 | 1 | T23 | 443 | T35 | 422 | T36 | 403 | ||||
others[2] | 34778 | 1 | T23 | 383 | T35 | 412 | T36 | 383 | ||||
others[3] | 58844 | 1 | T23 | 656 | T35 | 646 | T14 | 1 | ||||
false | 20064 | 1 | T9 | 38 | T12 | 82 | T23 | 50 | ||||
true | 30077 | 1 | T1 | 2 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35124 | 1 | T23 | 403 | T35 | 425 | T36 | 418 | ||||
others[1] | 34917 | 1 | T23 | 380 | T35 | 401 | T36 | 400 | ||||
others[2] | 35212 | 1 | T23 | 409 | T35 | 415 | T36 | 393 | ||||
others[3] | 58164 | 1 | T23 | 654 | T35 | 649 | T36 | 649 | ||||
false | 12621 | 1 | T9 | 19 | T12 | 41 | T23 | 50 | ||||
true | 22701 | 1 | T1 | 2 | T2 | 1 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 681 | 1 | T3 | 4 | T5 | 5 | T7 | 7 | ||||
others[1] | 721 | 1 | T3 | 6 | T5 | 6 | T7 | 4 | ||||
others[2] | 716 | 1 | T3 | 9 | T5 | 8 | T7 | 7 | ||||
others[3] | 1135 | 1 | T3 | 6 | T5 | 8 | T7 | 9 | ||||
false | 13627 | 1 | T1 | 2 | T2 | 1 | T3 | 4 | ||||
true | 3978 | 1 | T3 | 1 | T7 | 2 | T12 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |