Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T40,T23

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	24012681	6474	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	24012681	266274	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	24012681	9864887	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	24012681	266271	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	24012681	6474	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	24012681	266274	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	24012681	9864887	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	24012681	266271	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	6474	0	0
T8	2333	1	0	0
T9	12120	9	0	0
T10	3160	0	0	0
T11	792	0	0	0
T12	56944	22	0	0
T13	56390	10	0	0
T23	21232	22	0	0
T35	0	22	0	0
T36	0	24	0	0
T38	0	21	0	0
T39	2311	1	0	0
T40	1340	3	0	0
T41	5129	0	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	266274	0	0
T8	2333	13	0	0
T9	12120	239	0	0
T10	3160	0	0	0
T11	792	0	0	0
T12	56944	1340	0	0
T13	56390	373	0	0
T23	21232	516	0	0
T35	0	865	0	0
T36	0	451	0	0
T38	0	774	0	0
T39	2311	10	0	0
T40	1340	224	0	0
T41	5129	0	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	9864887	0	0
T2	14985	8570	0	0
T3	1978	0	0	0
T4	15795	0	0	0
T5	2544	0	0	0
T6	834	0	0	0
T7	4407	0	0	0
T8	2333	1417	0	0
T9	12120	6142	0	0
T10	3160	0	0	0
T12	56944	27967	0	0
T13	0	18133	0	0
T23	0	10057	0	0
T35	0	18335	0	0
T39	0	1465	0	0
T40	0	684	0	0
T41	0	1958	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	266271	0	0
T8	2333	13	0	0
T9	12120	239	0	0
T10	3160	0	0	0
T11	792	0	0	0
T12	56944	1340	0	0
T13	56390	373	0	0
T23	21232	516	0	0
T35	0	865	0	0
T36	0	451	0	0
T38	0	774	0	0
T39	2311	10	0	0
T40	1340	224	0	0
T41	5129	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	6474	0	0
T8	2333	1	0	0
T9	12120	9	0	0
T10	3160	0	0	0
T11	792	0	0	0
T12	56944	22	0	0
T13	56390	10	0	0
T23	21232	22	0	0
T35	0	22	0	0
T36	0	24	0	0
T38	0	21	0	0
T39	2311	1	0	0
T40	1340	3	0	0
T41	5129	0	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	266274	0	0
T8	2333	13	0	0
T9	12120	239	0	0
T10	3160	0	0	0
T11	792	0	0	0
T12	56944	1340	0	0
T13	56390	373	0	0
T23	21232	516	0	0
T35	0	865	0	0
T36	0	451	0	0
T38	0	774	0	0
T39	2311	10	0	0
T40	1340	224	0	0
T41	5129	0	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	9864887	0	0
T2	14985	8570	0	0
T3	1978	0	0	0
T4	15795	0	0	0
T5	2544	0	0	0
T6	834	0	0	0
T7	4407	0	0	0
T8	2333	1417	0	0
T9	12120	6142	0	0
T10	3160	0	0	0
T12	56944	27967	0	0
T13	0	18133	0	0
T23	0	10057	0	0
T35	0	18335	0	0
T39	0	1465	0	0
T40	0	684	0	0
T41	0	1958	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	266271	0	0
T8	2333	13	0	0
T9	12120	239	0	0
T10	3160	0	0	0
T11	792	0	0	0
T12	56944	1340	0	0
T13	56390	373	0	0
T23	21232	516	0	0
T35	0	865	0	0
T36	0	451	0	0
T38	0	774	0	0
T39	2311	10	0	0
T40	1340	224	0	0
T41	5129	0	0	0