Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24602231	15279	0	0
intr_enable_rd_A	24602231	42130	0	0
reset_en_rd_A	24602231	1246	0	0
reset_en_regwen_rd_A	24602231	1094	0	0
wake_info_capture_dis_rd_A	24602231	1048	0	0
wakeup_en_rd_A	24602231	1603	0	0
wakeup_en_regwen_rd_A	24602231	1028	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24602231	15279	0	0
T13	56390	21	0	0
T14	2931	0	0	0
T15	393306	47	0	0
T20	0	9	0	0
T21	3129	0	0	0
T31	0	19	0	0
T35	38628	0	0	0
T36	19603	0	0	0
T37	3081	0	0	0
T38	36514	0	0	0
T41	5129	0	0	0
T43	7664	0	0	0
T70	0	2	0	0
T76	0	32	0	0
T135	0	38	0	0
T136	0	2	0	0
T137	0	15	0	0
T138	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24602231	42130	0	0
T7	4407	104	0	0
T8	2333	0	0	0
T9	12120	0	0	0
T10	3160	0	0	0
T11	792	0	0	0
T12	56944	0	0	0
T13	56390	0	0	0
T23	21232	0	0	0
T35	0	162	0	0
T36	0	179	0	0
T38	0	198	0	0
T39	2311	0	0	0
T40	1340	0	0	0
T74	0	58	0	0
T75	0	66	0	0
T95	0	16	0	0
T98	0	16	0	0
T139	0	59	0	0
T140	0	13	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24602231	1246	0	0
T20	419456	7	0	0
T70	0	6	0	0
T81	0	7	0	0
T132	1685	0	0	0
T133	14369	0	0	0
T137	0	10	0	0
T141	0	7	0	0
T142	0	13	0	0
T143	0	8	0	0
T144	0	4	0	0
T145	0	1	0	0
T146	0	3	0	0
T147	2163	0	0	0
T148	1896	0	0	0
T149	5513	0	0	0
T150	51082	0	0	0
T151	3410	0	0	0
T152	6082	0	0	0
T153	3039	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24602231	1094	0	0
T20	419456	6	0	0
T70	0	15	0	0
T71	0	3	0	0
T81	0	8	0	0
T132	1685	0	0	0
T133	14369	0	0	0
T137	0	7	0	0
T141	0	3	0	0
T142	0	7	0	0
T143	0	2	0	0
T144	0	4	0	0
T147	2163	0	0	0
T148	1896	0	0	0
T149	5513	0	0	0
T150	51082	0	0	0
T151	3410	0	0	0
T152	6082	0	0	0
T153	3039	0	0	0
T154	0	15	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24602231	1048	0	0
T20	419456	11	0	0
T70	0	8	0	0
T71	0	6	0	0
T81	0	13	0	0
T132	1685	0	0	0
T133	14369	0	0	0
T137	0	2	0	0
T141	0	2	0	0
T142	0	4	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	2163	0	0	0
T148	1896	0	0	0
T149	5513	0	0	0
T150	51082	0	0	0
T151	3410	0	0	0
T152	6082	0	0	0
T153	3039	0	0	0
T154	0	10	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24602231	1603	0	0
T20	419456	3	0	0
T70	0	10	0	0
T77	0	5	0	0
T81	0	2	0	0
T132	1685	0	0	0
T133	14369	0	0	0
T137	0	1	0	0
T141	0	4	0	0
T142	0	11	0	0
T143	0	1	0	0
T145	0	1	0	0
T146	0	5	0	0
T147	2163	0	0	0
T148	1896	0	0	0
T149	5513	0	0	0
T150	51082	0	0	0
T151	3410	0	0	0
T152	6082	0	0	0
T153	3039	0	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24602231	1028	0	0
T20	419456	10	0	0
T50	0	9	0	0
T70	0	12	0	0
T81	0	12	0	0
T94	0	4	0	0
T132	1685	0	0	0
T133	14369	0	0	0
T142	0	6	0	0
T143	0	7	0	0
T144	0	7	0	0
T146	0	6	0	0
T147	2163	0	0	0
T148	1896	0	0	0
T149	5513	0	0	0
T150	51082	0	0	0
T151	3410	0	0	0
T152	6082	0	0	0
T153	3039	0	0	0
T154	0	15	0	0