Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	24012681	54756	0	0
IoStatusRise_A	24012681	60880	0	0
MainStatusFall_A	24012681	54756	0	0
MainStatusRise_A	24012681	60880	0	0
UsbStatusFall_A	24012681	37807	0	0
UsbStatusRise_A	24012681	42484	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	54756	0	0
T2	14985	16	0	0
T3	1978	1	0	0
T4	15795	5	0	0
T5	2544	0	0	0
T6	834	1	0	0
T7	4407	2	0	0
T8	2333	2	0	0
T9	12120	31	0	0
T10	3160	0	0	0
T12	56944	110	0	0
T39	0	2	0	0
T40	0	4	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	60880	0	0
T1	1011	2	0	0
T2	14985	17	0	0
T3	1978	2	0	0
T4	15795	6	0	0
T5	2544	1	0	0
T6	834	3	0	0
T7	4407	3	0	0
T8	2333	3	0	0
T9	12120	32	0	0
T10	3160	5	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	54756	0	0
T2	14985	16	0	0
T3	1978	1	0	0
T4	15795	5	0	0
T5	2544	0	0	0
T6	834	1	0	0
T7	4407	2	0	0
T8	2333	2	0	0
T9	12120	31	0	0
T10	3160	0	0	0
T12	56944	110	0	0
T39	0	2	0	0
T40	0	4	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	60880	0	0
T1	1011	2	0	0
T2	14985	17	0	0
T3	1978	2	0	0
T4	15795	6	0	0
T5	2544	1	0	0
T6	834	3	0	0
T7	4407	3	0	0
T8	2333	3	0	0
T9	12120	32	0	0
T10	3160	5	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	37807	0	0
T2	14985	13	0	0
T3	1978	1	0	0
T4	15795	5	0	0
T5	2544	0	0	0
T6	834	1	0	0
T7	4407	2	0	0
T8	2333	2	0	0
T9	12120	18	0	0
T10	3160	0	0	0
T12	56944	76	0	0
T39	0	2	0	0
T40	0	4	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	42484	0	0
T1	1011	2	0	0
T2	14985	13	0	0
T3	1978	2	0	0
T4	15795	6	0	0
T5	2544	1	0	0
T6	834	3	0	0
T7	4407	3	0	0
T8	2333	3	0	0
T9	12120	18	0	0
T10	3160	5	0	0