Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	24013257	7176	0	0
EscTimeoutStoppedByClReset_A	24012681	3414069	0	0
EscTimeoutTriggersReset_A	5015297	315	0	0
RomAllowActiveState_A	24012681	60514	0	0
RomAllowCheckGoodState_A	24012681	60565	0	0
RomBlockActiveState_A	24012681	31477	0	0
RomBlockCheckGoodState_A	24012681	431571	0	0
RomIntgChkDisFalse_A	24012681	23385831	0	0
RomIntgChkDisTrue_A	24012681	99866	0	0
RstreqChkEsctimeout_A	24012681	4407	0	0
RstreqChkFsmterm_A	24012681	140	0	0
RstreqChkGlbesc_A	24012681	4407	0	0
RstreqChkMainpd_A	24012681	989803	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24013257	7176	0	0
T4	15796	118	0	0
T5	2544	0	0	0
T6	835	0	0	0
T7	4408	0	0	0
T8	2334	0	0	0
T9	12121	0	0	0
T10	3161	0	0	0
T11	0	1	0	0
T12	56944	0	0	0
T39	2311	0	0	0
T40	1341	0	0	0
T42	0	157	0	0
T89	0	33	0	0
T155	0	31	0	0
T156	0	187	0	0
T157	0	175	0	0
T158	0	196	0	0
T159	0	271	0	0
T160	0	169	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	3414069	0	0
T2	14985	2385	0	0
T3	1978	15	0	0
T4	15795	55	0	0
T5	2544	2	0	0
T6	834	24	0	0
T7	4407	36	0	0
T8	2333	13	0	0
T9	12120	2100	0	0
T10	3160	25	0	0
T12	56944	9480	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5015297	315	0	0
T4	194	2	0	0
T5	1506	0	0	0
T6	269	5	0	0
T7	1303	0	0	0
T8	203	0	0	0
T9	2711	0	0	0
T10	317	0	0	0
T11	0	4	0	0
T12	5430	0	0	0
T39	212	0	0	0
T40	573	0	0	0
T42	0	2	0	0
T97	0	4	0	0
T155	0	2	0	0
T161	0	5	0	0
T162	0	6	0	0
T163	0	4	0	0
T164	0	3	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	60514	0	0
T1	1011	2	0	0
T2	14985	17	0	0
T3	1978	2	0	0
T4	15795	6	0	0
T5	2544	1	0	0
T6	834	3	0	0
T7	4407	3	0	0
T8	2333	3	0	0
T9	12120	32	0	0
T10	3160	5	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	60565	0	0
T1	1011	2	0	0
T2	14985	17	0	0
T3	1978	2	0	0
T4	15795	6	0	0
T5	2544	1	0	0
T6	834	3	0	0
T7	4407	3	0	0
T8	2333	3	0	0
T9	12120	32	0	0
T10	3160	5	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	31477	0	0
T13	56390	0	0	0
T14	2931	688	0	0
T15	393306	0	0	0
T21	3129	566	0	0
T22	0	456	0	0
T23	21232	10	0	0
T35	38628	0	0	0
T36	19603	6	0	0
T37	3081	0	0	0
T38	36514	0	0	0
T41	5129	0	0	0
T165	0	5	0	0
T166	0	13	0	0
T167	0	17	0	0
T168	0	15	0	0
T169	0	3	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	431571	0	0
T9	12120	436	0	0
T10	3160	0	0	0
T11	792	0	0	0
T12	56944	941	0	0
T13	56390	296	0	0
T14	0	317	0	0
T15	0	1491	0	0
T21	0	323	0	0
T23	21232	1183	0	0
T35	38628	2281	0	0
T36	0	829	0	0
T38	0	2317	0	0
T39	2311	0	0	0
T40	1340	0	0	0
T41	5129	0	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	23385831	0	0
T1	1011	843	0	0
T2	14985	14909	0	0
T3	1978	1890	0	0
T4	15795	15704	0	0
T5	2544	2478	0	0
T6	834	698	0	0
T7	4407	4340	0	0
T8	2333	2233	0	0
T9	12120	12025	0	0
T10	3160	2768	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	99866	0	0
T14	2931	1078	0	0
T15	393306	0	0	0
T21	3129	1017	0	0
T22	3102	353	0	0
T36	19603	0	0	0
T37	3081	0	0	0
T38	36514	0	0	0
T43	7664	0	0	0
T74	9911	0	0	0
T100	0	329	0	0
T165	0	431	0	0
T166	0	810	0	0
T167	0	383	0	0
T168	0	24	0	0
T170	0	728	0	0
T171	0	215	0	0
T172	47511	0	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	4407	0	0
T4	15795	1	0	0
T5	2544	0	0	0
T6	834	1	0	0
T7	4407	0	0	0
T8	2333	0	0	0
T9	12120	0	0	0
T10	3160	0	0	0
T11	0	1	0	0
T12	56944	5	0	0
T13	0	16	0	0
T14	0	4	0	0
T15	0	59	0	0
T21	0	2	0	0
T37	0	6	0	0
T39	2311	0	0	0
T40	1340	0	0	0
T43	0	1	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	140	0	0
T17	12634	20	0	0
T18	0	40	0	0
T19	0	20	0	0
T24	0	20	0	0
T25	0	40	0	0
T26	5480	0	0	0
T27	1650	0	0	0
T28	54218	0	0	0
T29	48361	0	0	0
T30	15059	0	0	0
T31	410118	0	0	0
T32	1388	0	0	0
T33	1221	0	0	0
T34	4376	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	4407	0	0
T4	15795	1	0	0
T5	2544	0	0	0
T6	834	1	0	0
T7	4407	0	0	0
T8	2333	0	0	0
T9	12120	0	0	0
T10	3160	0	0	0
T11	0	1	0	0
T12	56944	5	0	0
T13	0	16	0	0
T14	0	4	0	0
T15	0	59	0	0
T21	0	2	0	0
T37	0	6	0	0
T39	2311	0	0	0
T40	1340	0	0	0
T43	0	1	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24012681	989803	0	0
T1	1011	6	0	0
T2	14985	0	0	0
T3	1978	0	0	0
T4	15795	0	0	0
T5	2544	0	0	0
T6	834	0	0	0
T7	4407	0	0	0
T8	2333	0	0	0
T9	12120	774	0	0
T10	3160	21	0	0
T12	0	4900	0	0
T13	0	1729	0	0
T14	0	357	0	0
T23	0	1449	0	0
T35	0	3516	0	0
T36	0	1418	0	0
T37	0	99	0	0