Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	532030	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

203537

1

T1

15

T2

195

T3

56

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	380930	1			T1	43		T2	406		T3	107
values[0x0]	177301	1			T1	10		T2	233		T3	53
values[0x1]	177336	1			T1	12		T2	219		T3	59

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	421243	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

314324

1

T1

29

T2

325

T3

85

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3693	1			T2	6		T3	2		T5	5
valid_sources[0x01]	3494	1			T5	1		T15	10		T16	34
valid_sources[0x02]	4346	1			T2	4		T3	2		T5	2
valid_sources[0x03]	2636	1			T2	1		T3	1		T10	1
valid_sources[0x04]	2468	1			T2	1		T5	3		T54	3
valid_sources[0x05]	3595	1			T2	1		T5	8		T54	2
valid_sources[0x06]	3380	1			T2	2		T5	2		T40	1
valid_sources[0x07]	2878	1			T5	9		T10	1		T40	1
valid_sources[0x08]	2196	1			T2	5		T5	1		T54	1
valid_sources[0x09]	4172	1			T2	3		T5	1		T54	1
valid_sources[0x0a]	2191	1			T2	2		T3	1		T5	5
valid_sources[0x0b]	2586	1			T1	1		T2	6		T3	2
valid_sources[0x0c]	2271	1			T2	3		T5	2		T15	8
valid_sources[0x0d]	2925	1			T2	6		T3	4		T5	2
valid_sources[0x0e]	5407	1			T1	1		T2	3		T3	1
valid_sources[0x0f]	3773	1			T2	6		T3	1		T5	1
valid_sources[0x10]	2175	1			T2	14		T3	4		T5	7
valid_sources[0x11]	2274	1			T1	4		T5	3		T10	1
valid_sources[0x12]	2718	1			T3	3		T5	6		T7	40
valid_sources[0x13]	2529	1			T15	8		T16	19		T35	1
valid_sources[0x14]	2640	1			T2	1		T3	1		T5	10
valid_sources[0x15]	2594	1			T2	12		T5	3		T54	4
valid_sources[0x16]	3075	1			T2	3		T3	1		T5	9
valid_sources[0x17]	3237	1			T3	1		T5	7		T15	10
valid_sources[0x18]	3954	1			T2	1		T3	3		T5	1
valid_sources[0x19]	3464	1			T2	1		T3	1		T5	1
valid_sources[0x1a]	1982	1			T5	1		T54	1		T15	13
valid_sources[0x1b]	2714	1			T2	1		T10	1		T54	2
valid_sources[0x1c]	2105	1			T5	2		T54	2		T15	4
valid_sources[0x1d]	2263	1			T2	13		T3	4		T5	1
valid_sources[0x1e]	2876	1			T1	1		T2	9		T3	1
valid_sources[0x1f]	2115	1			T3	1		T54	1		T15	11
valid_sources[0x20]	3358	1			T2	2		T5	1		T10	1
valid_sources[0x21]	2379	1			T2	1		T3	1		T5	4
valid_sources[0x22]	3352	1			T3	1		T54	3		T15	8
valid_sources[0x23]	2306	1			T5	7		T6	28		T40	1
valid_sources[0x24]	2234	1			T1	1		T2	6		T5	5
valid_sources[0x25]	2169	1			T2	1		T5	1		T54	1
valid_sources[0x26]	2413	1			T2	2		T3	1		T5	2
valid_sources[0x27]	2390	1			T3	2		T5	4		T54	1
valid_sources[0x28]	3521	1			T5	3		T40	1		T54	4
valid_sources[0x29]	2230	1			T1	1		T3	1		T5	5
valid_sources[0x2a]	2373	1			T6	2		T40	2		T15	9
valid_sources[0x2b]	2957	1			T1	4		T5	4		T10	2
valid_sources[0x2c]	2282	1			T2	1		T3	2		T5	2
valid_sources[0x2d]	3417	1			T5	1		T54	2		T15	14
valid_sources[0x2e]	2409	1			T1	2		T2	1		T3	1
valid_sources[0x2f]	2602	1			T3	2		T5	1		T54	1
valid_sources[0x30]	2207	1			T5	6		T54	2		T15	10
valid_sources[0x31]	2604	1			T2	2		T3	1		T5	2
valid_sources[0x32]	3469	1			T2	2		T5	1		T54	1
valid_sources[0x33]	2316	1			T2	10		T5	4		T54	2
valid_sources[0x34]	2231	1			T2	1		T3	1		T5	8
valid_sources[0x35]	2174	1			T2	3		T5	4		T15	9
valid_sources[0x36]	2175	1			T1	2		T2	6		T5	8
valid_sources[0x37]	3398	1			T2	8		T3	1		T5	4
valid_sources[0x38]	2058	1			T1	1		T54	3		T15	6
valid_sources[0x39]	3585	1			T2	1		T3	3		T10	1
valid_sources[0x3a]	2208	1			T2	6		T3	1		T5	11
valid_sources[0x3b]	2372	1			T2	14		T5	1		T15	6
valid_sources[0x3c]	2748	1			T2	7		T3	1		T54	3
valid_sources[0x3d]	4795	1			T3	1		T5	1		T54	1
valid_sources[0x3e]	2940	1			T5	2		T6	8		T10	2
valid_sources[0x3f]	2217	1			T2	8		T3	1		T40	1
valid_sources[0x40]	2661	1			T2	2		T3	1		T5	5
valid_sources[0x41]	2259	1			T2	4		T3	2		T5	9
valid_sources[0x42]	2087	1			T2	1		T3	1		T5	4
valid_sources[0x43]	2227	1			T2	3		T3	4		T5	1
valid_sources[0x44]	4200	1			T5	2		T54	1		T15	7
valid_sources[0x45]	2048	1			T5	4		T15	11		T16	18
valid_sources[0x46]	2687	1			T2	1		T5	3		T6	3
valid_sources[0x47]	3116	1			T2	11		T5	3		T40	1
valid_sources[0x48]	3726	1			T2	1		T5	1		T54	2
valid_sources[0x49]	2238	1			T2	6		T3	1		T5	4
valid_sources[0x4a]	2546	1			T5	4		T15	9		T16	15
valid_sources[0x4b]	2255	1			T2	4		T3	2		T54	5
valid_sources[0x4c]	2408	1			T2	3		T15	6		T16	14
valid_sources[0x4d]	4127	1			T2	3		T3	2		T5	2
valid_sources[0x4e]	2963	1			T1	1		T3	1		T5	6
valid_sources[0x4f]	2522	1			T2	7		T5	7		T6	4
valid_sources[0x50]	2154	1			T3	1		T5	3		T54	1
valid_sources[0x51]	2510	1			T2	1		T5	7		T6	2
valid_sources[0x52]	2454	1			T1	4		T3	1		T5	1
valid_sources[0x53]	2293	1			T2	3		T5	8		T54	2
valid_sources[0x54]	5053	1			T2	2		T5	5		T54	1
valid_sources[0x55]	3057	1			T2	3		T5	7		T10	2
valid_sources[0x56]	3093	1			T2	11		T3	1		T5	5
valid_sources[0x57]	2191	1			T2	7		T5	8		T40	1
valid_sources[0x58]	2118	1			T2	12		T5	1		T54	5
valid_sources[0x59]	2754	1			T3	1		T5	5		T54	1
valid_sources[0x5a]	3140	1			T3	1		T5	6		T15	8
valid_sources[0x5b]	2678	1			T2	4		T15	12		T16	18
valid_sources[0x5c]	2115	1			T1	1		T2	3		T3	1
valid_sources[0x5d]	2456	1			T2	4		T3	1		T5	2
valid_sources[0x5e]	2214	1			T5	4		T54	1		T15	6
valid_sources[0x5f]	3303	1			T2	1		T5	8		T10	1
valid_sources[0x60]	2139	1			T54	1		T15	15		T16	15
valid_sources[0x61]	2699	1			T2	5		T54	2		T15	18
valid_sources[0x62]	2429	1			T2	10		T5	2		T15	13
valid_sources[0x63]	2426	1			T5	1		T10	2		T54	1
valid_sources[0x64]	3500	1			T2	2		T3	2		T5	1
valid_sources[0x65]	2215	1			T2	1		T3	1		T5	1
valid_sources[0x66]	2674	1			T2	2		T3	1		T5	4
valid_sources[0x67]	2226	1			T5	3		T15	16		T16	32
valid_sources[0x68]	2632	1			T2	15		T3	3		T5	4
valid_sources[0x69]	2163	1			T2	2		T5	1		T15	15
valid_sources[0x6a]	3251	1			T10	2		T54	3		T15	10
valid_sources[0x6b]	2313	1			T1	1		T2	4		T5	13
valid_sources[0x6c]	2669	1			T54	3		T15	4		T16	19
valid_sources[0x6d]	2263	1			T2	11		T5	1		T54	1
valid_sources[0x6e]	2493	1			T2	4		T3	3		T5	11
valid_sources[0x6f]	2202	1			T1	2		T2	3		T6	3
valid_sources[0x70]	2929	1			T2	2		T3	2		T54	1
valid_sources[0x71]	3746	1			T1	1		T2	1		T3	1
valid_sources[0x72]	2774	1			T3	1		T5	2		T6	1
valid_sources[0x73]	2204	1			T2	5		T3	1		T5	2
valid_sources[0x74]	2709	1			T2	2		T15	15		T16	16
valid_sources[0x75]	2087	1			T3	1		T15	10		T16	13
valid_sources[0x76]	2089	1			T2	6		T5	1		T10	2
valid_sources[0x77]	15515	1			T1	1		T2	14		T3	1
valid_sources[0x78]	2462	1			T3	2		T5	9		T15	7
valid_sources[0x79]	3450	1			T2	17		T3	1		T15	10
valid_sources[0x7a]	2666	1			T2	4		T3	1		T5	2
valid_sources[0x7b]	2662	1			T2	7		T3	1		T54	1
valid_sources[0x7c]	2343	1			T2	7		T5	9		T10	1
valid_sources[0x7d]	2710	1			T3	3		T5	3		T54	1
valid_sources[0x7e]	2136	1			T1	2		T3	2		T5	2
valid_sources[0x7f]	3468	1			T2	3		T3	2		T5	8
valid_sources[0x80]	2101	1			T2	2		T3	2		T5	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

101177

1

T1

12

T2

83

T3

36

values[0x0]

all_enables

biggest_size

66342

1

T1

2

T2

69

T3

12

values[0x1]

all_enables

biggest_size

36018

1

T1

1

T2

43

T3

8