SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 35243 | 1 | T2 | 300 | T5 | 420 | T9 | 1 | ||||
others[1] | 35383 | 1 | T2 | 306 | T5 | 381 | T35 | 293 | ||||
others[2] | 34945 | 1 | T1 | 1 | T2 | 301 | T5 | 394 | ||||
others[3] | 58193 | 1 | T2 | 490 | T5 | 683 | T35 | 488 | ||||
false | 19689 | 1 | T1 | 3 | T2 | 50 | T5 | 50 | ||||
true | 29843 | 1 | T1 | 3 | T2 | 51 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34920 | 1 | T2 | 305 | T5 | 419 | T9 | 1 | ||||
others[1] | 35428 | 1 | T2 | 301 | T5 | 391 | T35 | 279 | ||||
others[2] | 34924 | 1 | T1 | 1 | T2 | 299 | T5 | 400 | ||||
others[3] | 58343 | 1 | T2 | 497 | T5 | 654 | T35 | 493 | ||||
false | 12442 | 1 | T1 | 1 | T2 | 50 | T5 | 50 | ||||
true | 22659 | 1 | T1 | 3 | T2 | 51 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 689 | 1 | T23 | 2 | T14 | 1 | T15 | 1 | ||||
others[1] | 675 | 1 | T1 | 1 | T23 | 6 | T14 | 3 | ||||
others[2] | 711 | 1 | T9 | 1 | T23 | 9 | T14 | 5 | ||||
others[3] | 1155 | 1 | T1 | 1 | T23 | 8 | T14 | 2 | ||||
false | 13913 | 1 | T1 | 5 | T2 | 1 | T3 | 1 | ||||
true | 4173 | 1 | T1 | 2 | T9 | 3 | T23 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |