Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T10,T40

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	23302997	6510	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	23302997	250585	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	23302997	9635877	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	23302997	250544	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	23302997	6510	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	23302997	250585	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	23302997	9635877	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	23302997	250544	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23302997	6510	0	0
T2	34779	21	0	0
T3	3651	0	0	0
T4	565	0	0	0
T5	26330	25	0	0
T6	17497	0	0	0
T7	1630	4	0	0
T8	2400	0	0	0
T9	1724	0	0	0
T10	3257	3	0	0
T15	0	9	0	0
T16	0	47	0	0
T21	0	40	0	0
T23	2338	0	0	0
T35	0	22	0	0
T40	0	1	0	0
T73	0	11	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23302997	250585	0	0
T2	34779	941	0	0
T3	3651	0	0	0
T4	565	0	0	0
T5	26330	568	0	0
T6	17497	0	0	0
T7	1630	352	0	0
T8	2400	0	0	0
T9	1724	0	0	0
T10	3257	630	0	0
T15	0	356	0	0
T16	0	1541	0	0
T21	0	951	0	0
T23	2338	0	0	0
T35	0	732	0	0
T40	0	115	0	0
T73	0	202	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23302997	9635877	0	0
T2	34779	16262	0	0
T3	3651	453	0	0
T4	565	0	0	0
T5	26330	13217	0	0
T6	17497	8001	0	0
T7	1630	971	0	0
T8	2400	0	0	0
T9	1724	0	0	0
T10	3257	1181	0	0
T14	0	10558	0	0
T23	2338	0	0	0
T40	0	106	0	0
T51	0	7088	0	0
T54	0	6561	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23302997	250544	0	0
T2	34779	941	0	0
T3	3651	0	0	0
T4	565	0	0	0
T5	26330	568	0	0
T6	17497	0	0	0
T7	1630	352	0	0
T8	2400	0	0	0
T9	1724	0	0	0
T10	3257	630	0	0
T15	0	356	0	0
T16	0	1546	0	0
T21	0	955	0	0
T23	2338	0	0	0
T35	0	730	0	0
T40	0	115	0	0
T73	0	202	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23302997	6510	0	0
T2	34779	21	0	0
T3	3651	0	0	0
T4	565	0	0	0
T5	26330	25	0	0
T6	17497	0	0	0
T7	1630	4	0	0
T8	2400	0	0	0
T9	1724	0	0	0
T10	3257	3	0	0
T15	0	9	0	0
T16	0	47	0	0
T21	0	40	0	0
T23	2338	0	0	0
T35	0	22	0	0
T40	0	1	0	0
T73	0	11	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23302997	250585	0	0
T2	34779	941	0	0
T3	3651	0	0	0
T4	565	0	0	0
T5	26330	568	0	0
T6	17497	0	0	0
T7	1630	352	0	0
T8	2400	0	0	0
T9	1724	0	0	0
T10	3257	630	0	0
T15	0	356	0	0
T16	0	1541	0	0
T21	0	951	0	0
T23	2338	0	0	0
T35	0	732	0	0
T40	0	115	0	0
T73	0	202	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23302997	9635877	0	0
T2	34779	16262	0	0
T3	3651	453	0	0
T4	565	0	0	0
T5	26330	13217	0	0
T6	17497	8001	0	0
T7	1630	971	0	0
T8	2400	0	0	0
T9	1724	0	0	0
T10	3257	1181	0	0
T14	0	10558	0	0
T23	2338	0	0	0
T40	0	106	0	0
T51	0	7088	0	0
T54	0	6561	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23302997	250544	0	0
T2	34779	941	0	0
T3	3651	0	0	0
T4	565	0	0	0
T5	26330	568	0	0
T6	17497	0	0	0
T7	1630	352	0	0
T8	2400	0	0	0
T9	1724	0	0	0
T10	3257	630	0	0
T15	0	356	0	0
T16	0	1546	0	0
T21	0	955	0	0
T23	2338	0	0	0
T35	0	730	0	0
T40	0	115	0	0
T73	0	202	0	0