Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	23859441	15311	0	0
intr_enable_rd_A	23859441	31896	0	0
reset_en_rd_A	23859441	1112	0	0
reset_en_regwen_rd_A	23859441	920	0	0
wake_info_capture_dis_rd_A	23859441	942	0	0
wakeup_en_rd_A	23859441	1845	0	0
wakeup_en_regwen_rd_A	23859441	848	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23859441	15311	0	0
T11	1229	0	0	0
T16	202287	5	0	0
T21	106796	8	0	0
T22	0	16	0	0
T35	32402	0	0	0
T36	3748	0	0	0
T37	1229	0	0	0
T38	98140	0	0	0
T39	8127	0	0	0
T46	0	45	0	0
T55	2646	0	0	0
T70	0	8	0	0
T73	8644	0	0	0
T123	0	8	0	0
T124	0	9	0	0
T125	0	29	0	0
T126	0	167	0	0
T127	0	24	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23859441	31896	0	0
T2	34779	102	0	0
T3	3651	0	0	0
T4	565	0	0	0
T5	26330	174	0	0
T6	17497	29	0	0
T7	1630	0	0	0
T8	2400	0	0	0
T9	1724	0	0	0
T10	3257	0	0	0
T14	0	225	0	0
T23	2338	0	0	0
T94	0	88	0	0
T128	0	34	0	0
T129	0	95	0	0
T130	0	22	0	0
T131	0	11	0	0
T132	0	78	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23859441	1112	0	0
T45	0	67	0	0
T63	0	5	0	0
T66	0	14	0	0
T70	111426	0	0	0
T89	0	5	0	0
T91	0	1	0	0
T114	0	42	0	0
T123	251600	1	0	0
T124	415700	0	0	0
T133	0	4	0	0
T134	0	2	0	0
T135	0	8	0	0
T136	2990	0	0	0
T137	25728	0	0	0
T138	9597	0	0	0
T139	1907	0	0	0
T140	15650	0	0	0
T141	3269	0	0	0
T142	14924	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23859441	920	0	0
T45	0	43	0	0
T63	0	6	0	0
T66	0	9	0	0
T89	0	8	0	0
T91	351189	11	0	0
T114	0	2	0	0
T133	0	8	0	0
T134	0	6	0	0
T135	0	6	0	0
T143	0	4	0	0
T144	7112	0	0	0
T145	3604	0	0	0
T146	1285	0	0	0
T147	2030	0	0	0
T148	2338	0	0	0
T149	50751	0	0	0
T150	19750	0	0	0
T151	2945	0	0	0
T152	56230	0	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23859441	942	0	0
T45	0	51	0	0
T66	0	2	0	0
T70	111426	0	0	0
T89	0	4	0	0
T91	0	9	0	0
T114	0	9	0	0
T116	0	6	0	0
T123	251600	1	0	0
T124	415700	0	0	0
T133	0	2	0	0
T135	0	1	0	0
T136	2990	0	0	0
T137	25728	0	0	0
T138	9597	0	0	0
T139	1907	0	0	0
T140	15650	0	0	0
T141	3269	0	0	0
T142	14924	0	0	0
T153	0	10	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23859441	1845	0	0
T45	0	134	0	0
T63	0	7	0	0
T66	0	33	0	0
T70	111426	0	0	0
T89	0	1	0	0
T91	0	9	0	0
T114	0	29	0	0
T123	251600	8	0	0
T124	415700	0	0	0
T133	0	2	0	0
T135	0	9	0	0
T136	2990	0	0	0
T137	25728	0	0	0
T138	9597	0	0	0
T139	1907	0	0	0
T140	15650	0	0	0
T141	3269	0	0	0
T142	14924	0	0	0
T153	0	86	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23859441	848	0	0
T45	0	25	0	0
T63	0	5	0	0
T66	0	8	0	0
T89	0	9	0	0
T91	351189	2	0	0
T114	0	37	0	0
T116	0	4	0	0
T135	0	4	0	0
T144	7112	0	0	0
T145	3604	0	0	0
T146	1285	0	0	0
T147	2030	0	0	0
T148	2338	0	0	0
T149	50751	0	0	0
T150	19750	0	0	0
T151	2945	0	0	0
T152	56230	0	0	0
T153	0	8	0	0
T154	0	5	0	0