Unified Coverage Report :: Module :: pwrmgr_sec_cm_checker_assert

Module : pwrmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	42	1	1	100.00
ALWAYS	43	1	1	100.00
ALWAYS	44	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_pwrmgr_sva_0.1/pwrmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
43	1	1
44	1	1

---

Cond Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       42
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       43
 EXPRESSION (((!rst_esc_ni)) || disable_sva)
             -------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       44
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
EscClkStopEscTimeout_A	23303580	5560	0	0
EscTimeoutStoppedByClReset_A	23302997	3205406	0	0
EscTimeoutTriggersReset_A	5143904	300	0	0
RomAllowActiveState_A	23302997	61725	0	0
RomAllowCheckGoodState_A	23302997	61776	0	0
RomBlockActiveState_A	23302997	30663	0	0
RomBlockCheckGoodState_A	23302997	436640	0	0
RomIntgChkDisFalse_A	23302997	22663392	0	0
RomIntgChkDisTrue_A	23302997	106416	0	0
RstreqChkEsctimeout_A	23302997	4434	0	0
RstreqChkFsmterm_A	23302997	120	0	0
RstreqChkGlbesc_A	23302997	4434	0	0
RstreqChkMainpd_A	23302997	945507	0	0

EscClkStopEscTimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23303580	5560	0	0
T13	613	4	0	0
T42	2958	0	0	0
T94	4884	0	0	0
T131	3340	0	0	0
T140	0	162	0	0
T142	0	56	0	0
T155	15534	129	0	0
T156	0	32	0	0
T157	0	216	0	0
T158	0	81	0	0
T159	0	129	0	0
T160	0	12	0	0
T161	0	14	0	0
T162	30382	0	0	0
T163	46446	0	0	0
T164	51940	0	0	0
T165	1359	0	0	0
T166	1231	0	0	0

EscTimeoutStoppedByClReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23302997	3205406	0	0
T1	2545	133	0	0
T2	34779	6145	0	0
T3	3651	7	0	0
T4	565	37	0	0
T5	26330	3114	0	0
T6	17497	3377	0	0
T7	1630	70	0	0
T8	2400	46	0	0
T9	1724	101	0	0
T10	3257	80	0	0

EscTimeoutTriggersReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5143904	300	0	0
T11	243	4	0	0
T12	290	5	0	0
T13	0	7	0	0
T41	1151	0	0	0
T128	1343	0	0	0
T129	1189	0	0	0
T140	0	2	0	0
T142	0	3	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	3	0	0
T158	0	3	0	0
T165	0	2	0	0
T167	1293	0	0	0
T168	2033	0	0	0
T169	3045	0	0	0
T170	1800	0	0	0
T171	311	0	0	0

RomAllowActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23302997	61725	0	0
T1	2545	7	0	0
T2	34779	88	0	0
T3	3651	15	0	0
T4	565	4	0	0
T5	26330	89	0	0
T6	17497	17	0	0
T7	1630	5	0	0
T8	2400	7	0	0
T9	1724	8	0	0
T10	3257	5	0	0

RomAllowCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23302997	61776	0	0
T1	2545	7	0	0
T2	34779	88	0	0
T3	3651	15	0	0
T4	565	4	0	0
T5	26330	89	0	0
T6	17497	17	0	0
T7	1630	5	0	0
T8	2400	7	0	0
T9	1724	8	0	0
T10	3257	5	0	0

RomBlockActiveState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23302997	30663	0	0
T1	2545	457	0	0
T2	34779	0	0	0
T3	3651	0	0	0
T4	565	0	0	0
T5	26330	19	0	0
T6	17497	0	0	0
T7	1630	0	0	0
T8	2400	0	0	0
T9	1724	198	0	0
T10	3257	0	0	0
T36	0	870	0	0
T37	0	55	0	0
T80	0	18	0	0
T172	0	25	0	0
T173	0	286	0	0
T174	0	240	0	0
T175	0	235	0	0

RomBlockCheckGoodState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23302997	436640	0	0
T1	2545	181	0	0
T2	34779	2215	0	0
T3	3651	0	0	0
T4	565	0	0	0
T5	26330	1362	0	0
T6	17497	0	0	0
T7	1630	0	0	0
T8	2400	0	0	0
T9	1724	85	0	0
T10	3257	0	0	0
T15	0	574	0	0
T16	0	2385	0	0
T21	0	1833	0	0
T35	0	2287	0	0
T36	0	341	0	0
T73	0	434	0	0

RomIntgChkDisFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23302997	22663392	0	0
T1	2545	1235	0	0
T2	34779	34421	0	0
T3	3651	3597	0	0
T4	565	280	0	0
T5	26330	26240	0	0
T6	17497	17406	0	0
T7	1630	1245	0	0
T8	2400	1835	0	0
T9	1724	1474	0	0
T10	3257	2857	0	0

RomIntgChkDisTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23302997	106416	0	0
T1	2545	1260	0	0
T2	34779	306	0	0
T3	3651	0	0	0
T4	565	0	0	0
T5	26330	0	0	0
T6	17497	0	0	0
T7	1630	0	0	0
T8	2400	0	0	0
T9	1724	85	0	0
T10	3257	0	0	0
T35	0	1348	0	0
T36	0	1393	0	0
T37	0	91	0	0
T132	0	3337	0	0
T163	0	622	0	0
T164	0	1138	0	0
T176	0	1553	0	0

RstreqChkEsctimeout_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23302997	4434	0	0
T1	2545	2	0	0
T2	34779	0	0	0
T3	3651	0	0	0
T4	565	0	0	0
T5	26330	0	0	0
T6	17497	0	0	0
T7	1630	0	0	0
T8	2400	0	0	0
T9	1724	4	0	0
T10	3257	0	0	0
T14	0	23	0	0
T15	0	13	0	0
T16	0	17	0	0
T21	0	71	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	15	0	0
T39	0	7	0	0

RstreqChkFsmterm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23302997	120	0	0
T18	15906	20	0	0
T19	0	20	0	0
T20	0	40	0	0
T24	0	20	0	0
T25	0	20	0	0
T26	15179	0	0	0
T27	1728	0	0	0
T28	1173	0	0	0
T29	1265	0	0	0
T30	54012	0	0	0
T31	3441	0	0	0
T32	5804	0	0	0
T33	15792	0	0	0
T34	2789	0	0	0

RstreqChkGlbesc_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23302997	4434	0	0
T1	2545	2	0	0
T2	34779	0	0	0
T3	3651	0	0	0
T4	565	0	0	0
T5	26330	0	0	0
T6	17497	0	0	0
T7	1630	0	0	0
T8	2400	0	0	0
T9	1724	4	0	0
T10	3257	0	0	0
T14	0	23	0	0
T15	0	13	0	0
T16	0	17	0	0
T21	0	71	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	15	0	0
T39	0	7	0	0

RstreqChkMainpd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23302997	945507	0	0
T1	2545	315	0	0
T2	34779	3934	0	0
T3	3651	0	0	0
T4	565	11	0	0
T5	26330	1859	0	0
T6	17497	0	0	0
T7	1630	0	0	0
T8	2400	27	0	0
T9	1724	98	0	0
T10	3257	0	0	0
T14	0	2343	0	0
T15	0	1659	0	0
T17	0	29	0	0
T177	0	11	0	0