Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_pwrmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	518079	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

199625

1

T1

22

T2

38

T3

38

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	376642	1			T1	50		T2	57		T3	126
values[0x0]	170305	1			T1	25		T2	20		T3	45
values[0x1]	170757	1			T1	25		T2	13		T3	37

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	410163	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

307541

1

T1

36

T2

40

T3

70

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3712	1			T3	3		T9	2		T24	3
valid_sources[0x01]	2640	1			T3	2		T6	1		T9	6
valid_sources[0x02]	2357	1			T3	4		T5	3		T6	1
valid_sources[0x03]	2384	1			T3	1		T9	5		T24	2
valid_sources[0x04]	3685	1			T6	2		T9	2		T24	3
valid_sources[0x05]	3625	1			T2	1		T9	3		T13	1
valid_sources[0x06]	2912	1			T3	1		T9	9		T24	3
valid_sources[0x07]	2574	1			T2	2		T6	3		T8	1
valid_sources[0x08]	2509	1			T2	1		T8	1		T9	4
valid_sources[0x09]	2682	1			T3	1		T9	4		T24	1
valid_sources[0x0a]	2673	1			T9	1		T13	2		T37	1
valid_sources[0x0b]	3087	1			T2	1		T9	3		T24	2
valid_sources[0x0c]	2456	1			T2	1		T6	1		T9	4
valid_sources[0x0d]	2729	1			T3	1		T9	1		T24	1
valid_sources[0x0e]	2567	1			T6	1		T9	6		T24	1
valid_sources[0x0f]	2807	1			T9	6		T24	2		T37	2
valid_sources[0x10]	2609	1			T2	2		T9	5		T24	10
valid_sources[0x11]	2573	1			T6	4		T8	1		T9	3
valid_sources[0x12]	2629	1			T2	1		T3	2		T6	3
valid_sources[0x13]	2567	1			T3	1		T9	8		T24	3
valid_sources[0x14]	2637	1			T3	2		T9	5		T13	2
valid_sources[0x15]	6523	1			T5	2		T9	2		T24	4
valid_sources[0x16]	2589	1			T2	2		T3	2		T9	3
valid_sources[0x17]	2441	1			T5	12		T9	3		T24	3
valid_sources[0x18]	2614	1			T3	1		T9	2		T24	1
valid_sources[0x19]	2330	1			T4	1		T9	4		T24	7
valid_sources[0x1a]	2584	1			T3	1		T5	1		T6	2
valid_sources[0x1b]	2688	1			T3	1		T5	1		T9	3
valid_sources[0x1c]	2881	1			T3	2		T6	1		T9	4
valid_sources[0x1d]	2653	1			T3	1		T6	1		T9	3
valid_sources[0x1e]	2294	1			T9	1		T24	1		T13	1
valid_sources[0x1f]	2497	1			T3	1		T5	2		T9	3
valid_sources[0x20]	3446	1			T2	1		T3	2		T9	5
valid_sources[0x21]	2702	1			T3	2		T4	2		T8	1
valid_sources[0x22]	2342	1			T3	1		T9	3		T24	3
valid_sources[0x23]	3506	1			T2	1		T4	1		T5	2
valid_sources[0x24]	3267	1			T24	6		T14	21		T16	35
valid_sources[0x25]	2565	1			T2	1		T3	2		T4	2
valid_sources[0x26]	2684	1			T2	1		T5	2		T9	7
valid_sources[0x27]	2451	1			T3	2		T8	1		T9	6
valid_sources[0x28]	2551	1			T3	4		T5	9		T6	4
valid_sources[0x29]	2575	1			T2	1		T3	1		T9	4
valid_sources[0x2a]	2574	1			T1	100		T2	1		T3	1
valid_sources[0x2b]	4454	1			T5	4		T9	2		T24	3
valid_sources[0x2c]	2584	1			T2	1		T3	1		T9	3
valid_sources[0x2d]	2445	1			T5	1		T9	3		T24	3
valid_sources[0x2e]	2703	1			T5	3		T9	4		T24	4
valid_sources[0x2f]	3907	1			T3	2		T4	1		T9	4
valid_sources[0x30]	2563	1			T2	1		T3	1		T9	3
valid_sources[0x31]	2772	1			T2	1		T3	1		T6	1
valid_sources[0x32]	2826	1			T2	1		T4	2		T9	2
valid_sources[0x33]	3721	1			T2	1		T5	1		T6	3
valid_sources[0x34]	3382	1			T2	1		T3	1		T5	6
valid_sources[0x35]	2422	1			T3	1		T5	1		T9	1
valid_sources[0x36]	2763	1			T4	2		T5	6		T6	1
valid_sources[0x37]	2877	1			T3	1		T6	2		T9	1
valid_sources[0x38]	2444	1			T4	1		T5	1		T6	1
valid_sources[0x39]	2713	1			T6	1		T9	1		T24	12
valid_sources[0x3a]	3517	1			T9	6		T11	1		T13	1
valid_sources[0x3b]	2404	1			T6	1		T9	5		T24	1
valid_sources[0x3c]	2631	1			T2	1		T6	2		T9	2
valid_sources[0x3d]	2705	1			T3	1		T8	1		T9	9
valid_sources[0x3e]	2442	1			T3	1		T6	1		T9	4
valid_sources[0x3f]	2922	1			T9	3		T13	1		T37	1
valid_sources[0x40]	2860	1			T6	2		T7	1		T8	1
valid_sources[0x41]	2542	1			T3	1		T5	1		T6	2
valid_sources[0x42]	2544	1			T3	2		T6	1		T9	4
valid_sources[0x43]	3348	1			T3	1		T9	4		T24	2
valid_sources[0x44]	2612	1			T6	1		T9	3		T24	2
valid_sources[0x45]	3689	1			T9	7		T24	6		T13	1
valid_sources[0x46]	2477	1			T5	9		T6	1		T9	5
valid_sources[0x47]	2313	1			T2	1		T5	4		T6	1
valid_sources[0x48]	2768	1			T9	5		T24	5		T13	2
valid_sources[0x49]	2691	1			T5	2		T6	2		T9	4
valid_sources[0x4a]	2641	1			T6	1		T9	5		T24	12
valid_sources[0x4b]	2639	1			T2	1		T5	1		T6	1
valid_sources[0x4c]	2605	1			T2	2		T3	2		T9	4
valid_sources[0x4d]	2691	1			T2	1		T9	1		T24	3
valid_sources[0x4e]	2418	1			T5	1		T9	4		T24	3
valid_sources[0x4f]	4666	1			T2	1		T5	2		T9	2
valid_sources[0x50]	2675	1			T3	1		T6	1		T7	4
valid_sources[0x51]	2832	1			T3	1		T5	8		T9	3
valid_sources[0x52]	2408	1			T3	1		T5	2		T6	1
valid_sources[0x53]	2563	1			T9	5		T24	1		T13	1
valid_sources[0x54]	2705	1			T5	9		T6	3		T9	10
valid_sources[0x55]	3205	1			T6	2		T9	2		T13	1
valid_sources[0x56]	2684	1			T2	1		T6	1		T9	3
valid_sources[0x57]	2706	1			T3	3		T6	1		T24	10
valid_sources[0x58]	2716	1			T3	2		T9	1		T24	7
valid_sources[0x59]	3454	1			T5	1		T9	4		T24	3
valid_sources[0x5a]	3195	1			T5	1		T9	2		T24	6
valid_sources[0x5b]	2625	1			T3	1		T5	9		T9	2
valid_sources[0x5c]	2671	1			T9	4		T24	1		T37	1
valid_sources[0x5d]	3432	1			T5	1		T9	2		T24	4
valid_sources[0x5e]	2622	1			T3	3		T9	3		T24	2
valid_sources[0x5f]	4518	1			T2	1		T3	2		T9	3
valid_sources[0x60]	2555	1			T2	1		T3	3		T6	1
valid_sources[0x61]	2592	1			T3	1		T5	1		T9	2
valid_sources[0x62]	3483	1			T2	2		T3	4		T5	1
valid_sources[0x63]	2679	1			T3	1		T6	1		T9	6
valid_sources[0x64]	2597	1			T3	2		T5	2		T9	4
valid_sources[0x65]	2562	1			T3	1		T5	5		T6	2
valid_sources[0x66]	2753	1			T2	2		T4	1		T9	1
valid_sources[0x67]	3297	1			T3	2		T6	1		T9	1
valid_sources[0x68]	2860	1			T3	1		T5	4		T6	3
valid_sources[0x69]	2510	1			T3	3		T4	2		T8	1
valid_sources[0x6a]	2507	1			T3	2		T6	2		T24	1
valid_sources[0x6b]	2953	1			T9	6		T24	1		T13	2
valid_sources[0x6c]	2387	1			T3	1		T5	2		T9	7
valid_sources[0x6d]	3416	1			T2	1		T5	3		T9	3
valid_sources[0x6e]	2562	1			T3	1		T4	1		T9	1
valid_sources[0x6f]	2426	1			T9	6		T24	5		T14	24
valid_sources[0x70]	2505	1			T3	1		T9	7		T24	6
valid_sources[0x71]	2481	1			T3	1		T9	1		T24	3
valid_sources[0x72]	4212	1			T6	1		T9	4		T24	1
valid_sources[0x73]	2416	1			T3	3		T5	5		T9	2
valid_sources[0x74]	2579	1			T4	1		T5	1		T9	4
valid_sources[0x75]	2478	1			T2	1		T6	1		T9	4
valid_sources[0x76]	2637	1			T3	2		T9	8		T24	4
valid_sources[0x77]	2437	1			T2	1		T5	4		T6	2
valid_sources[0x78]	2464	1			T3	1		T5	2		T9	2
valid_sources[0x79]	3346	1			T3	1		T5	4		T9	1
valid_sources[0x7a]	2605	1			T3	1		T5	3		T8	1
valid_sources[0x7b]	2496	1			T6	1		T9	1		T13	2
valid_sources[0x7c]	2497	1			T2	1		T3	1		T6	1
valid_sources[0x7d]	2685	1			T2	1		T24	5		T13	1
valid_sources[0x7e]	2634	1			T5	1		T6	2		T9	3
valid_sources[0x7f]	2863	1			T6	3		T9	1		T24	8
valid_sources[0x80]	2792	1			T6	2		T9	6		T24	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

101732

1

T1

9

T2

25

T3

15

values[0x0]

all_enables

biggest_size

63510

1

T1

7

T2

9

T3

18

values[0x1]

all_enables

biggest_size

34383

1

T1

6

T2

4

T3

5