SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_done_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_rom_ctrl_good_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_tb.dut.u_sw_rst_req_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34444 | 1 | T9 | 293 | T24 | 294 | T45 | 393 | ||||
others[1] | 34707 | 1 | T9 | 295 | T24 | 293 | T45 | 355 | ||||
others[2] | 34857 | 1 | T9 | 298 | T24 | 303 | T45 | 400 | ||||
others[3] | 58132 | 1 | T9 | 510 | T24 | 517 | T45 | 721 | ||||
false | 20222 | 1 | T9 | 50 | T24 | 50 | T14 | 34 | ||||
true | 30251 | 1 | T1 | 1 | T2 | 13 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 34726 | 1 | T9 | 295 | T24 | 296 | T45 | 409 | ||||
others[1] | 34569 | 1 | T9 | 303 | T24 | 309 | T45 | 401 | ||||
others[2] | 34776 | 1 | T9 | 317 | T24 | 294 | T45 | 407 | ||||
others[3] | 57982 | 1 | T9 | 497 | T24 | 510 | T45 | 651 | ||||
false | 12680 | 1 | T9 | 50 | T24 | 50 | T14 | 17 | ||||
true | 22775 | 1 | T1 | 1 | T2 | 13 | T3 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 692 | 1 | T2 | 2 | T3 | 4 | T13 | 3 | ||||
others[1] | 719 | 1 | T3 | 2 | T37 | 1 | T14 | 5 | ||||
others[2] | 669 | 1 | T14 | 6 | T38 | 2 | T16 | 1 | ||||
others[3] | 1143 | 1 | T2 | 1 | T3 | 2 | T14 | 8 | ||||
false | 13521 | 1 | T1 | 1 | T2 | 20 | T3 | 17 | ||||
true | 3916 | 1 | T2 | 4 | T3 | 8 | T13 | 6 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |