Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T43,T14

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	24208215	6492	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	24208215	269523	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	24208215	10008984	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	24208215	269498	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	24208215	6492	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	24208215	269523	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	24208215	10008984	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	24208215	269498	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	6492	0	0
T4	2869	1	0	0
T5	6932	0	0	0
T6	3983	0	0	0
T7	1995	0	0	0
T8	1088	0	0	0
T9	24023	23	0	0
T10	15206	0	0	0
T11	803	0	0	0
T14	0	14	0	0
T16	0	115	0	0
T24	18083	20	0	0
T42	1247	1	0	0
T43	0	1	0	0
T45	0	23	0	0
T72	0	1	0	0
T73	0	4	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	269523	0	0
T4	2869	195	0	0
T5	6932	0	0	0
T6	3983	0	0	0
T7	1995	0	0	0
T8	1088	0	0	0
T9	24023	489	0	0
T10	15206	0	0	0
T11	803	0	0	0
T14	0	838	0	0
T16	0	2905	0	0
T24	18083	388	0	0
T42	1247	13	0	0
T43	0	253	0	0
T45	0	387	0	0
T72	0	13	0	0
T73	0	62	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	10008984	0	0
T1	4464	1631	0	0
T2	8449	0	0	0
T3	5945	0	0	0
T4	2869	112	0	0
T5	6932	2906	0	0
T6	3983	1853	0	0
T7	1995	1159	0	0
T8	1088	0	0	0
T9	24023	11618	0	0
T10	15206	0	0	0
T14	0	71015	0	0
T24	0	7919	0	0
T42	0	942	0	0
T43	0	725	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	269498	0	0
T4	2869	195	0	0
T5	6932	0	0	0
T6	3983	0	0	0
T7	1995	0	0	0
T8	1088	0	0	0
T9	24023	489	0	0
T10	15206	0	0	0
T11	803	0	0	0
T14	0	838	0	0
T16	0	2901	0	0
T24	18083	388	0	0
T42	1247	13	0	0
T43	0	253	0	0
T45	0	387	0	0
T72	0	13	0	0
T73	0	62	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	6492	0	0
T4	2869	1	0	0
T5	6932	0	0	0
T6	3983	0	0	0
T7	1995	0	0	0
T8	1088	0	0	0
T9	24023	23	0	0
T10	15206	0	0	0
T11	803	0	0	0
T14	0	14	0	0
T16	0	115	0	0
T24	18083	20	0	0
T42	1247	1	0	0
T43	0	1	0	0
T45	0	23	0	0
T72	0	1	0	0
T73	0	4	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	269523	0	0
T4	2869	195	0	0
T5	6932	0	0	0
T6	3983	0	0	0
T7	1995	0	0	0
T8	1088	0	0	0
T9	24023	489	0	0
T10	15206	0	0	0
T11	803	0	0	0
T14	0	838	0	0
T16	0	2905	0	0
T24	18083	388	0	0
T42	1247	13	0	0
T43	0	253	0	0
T45	0	387	0	0
T72	0	13	0	0
T73	0	62	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	10008984	0	0
T1	4464	1631	0	0
T2	8449	0	0	0
T3	5945	0	0	0
T4	2869	112	0	0
T5	6932	2906	0	0
T6	3983	1853	0	0
T7	1995	1159	0	0
T8	1088	0	0	0
T9	24023	11618	0	0
T10	15206	0	0	0
T14	0	71015	0	0
T24	0	7919	0	0
T42	0	942	0	0
T43	0	725	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	269498	0	0
T4	2869	195	0	0
T5	6932	0	0	0
T6	3983	0	0	0
T7	1995	0	0	0
T8	1088	0	0	0
T9	24023	489	0	0
T10	15206	0	0	0
T11	803	0	0	0
T14	0	838	0	0
T16	0	2901	0	0
T24	18083	388	0	0
T42	1247	13	0	0
T43	0	253	0	0
T45	0	387	0	0
T72	0	13	0	0
T73	0	62	0	0