Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	24804931	15420	0	0
intr_enable_rd_A	24804931	30849	0	0
reset_en_rd_A	24804931	868	0	0
reset_en_regwen_rd_A	24804931	731	0	0
wake_info_capture_dis_rd_A	24804931	865	0	0
wakeup_en_rd_A	24804931	1333	0	0
wakeup_en_regwen_rd_A	24804931	745	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24804931	15420	0	0
T14	180031	37	0	0
T15	1466	0	0	0
T16	226356	6	0	0
T23	0	15	0	0
T25	4946	0	0	0
T33	0	79	0	0
T38	7698	0	0	0
T39	2901	0	0	0
T41	1539	0	0	0
T45	16001	0	0	0
T72	2353	0	0	0
T74	6334	0	0	0
T78	0	17	0	0
T87	0	79	0	0
T93	0	8	0	0
T139	0	27	0	0
T140	0	3	0	0
T141	0	44	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24804931	30849	0	0
T5	6932	63	0	0
T6	3983	0	0	0
T7	1995	0	0	0
T8	1088	0	0	0
T9	24023	106	0	0
T10	15206	0	0	0
T11	803	0	0	0
T13	6040	0	0	0
T23	0	1711	0	0
T24	18083	0	0	0
T25	0	22	0	0
T38	0	53	0	0
T41	0	13	0	0
T42	1247	12	0	0
T73	0	86	0	0
T76	0	9	0	0
T142	0	11	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24804931	868	0	0
T23	448695	8	0	0
T50	0	2	0	0
T77	3123	0	0	0
T78	0	12	0	0
T80	0	1	0	0
T93	0	3	0	0
T104	0	2	0	0
T106	2333	0	0	0
T107	3219	0	0	0
T108	6919	0	0	0
T137	48762	0	0	0
T142	1200	0	0	0
T143	0	2	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	6	0	0
T147	4192	0	0	0
T148	6564	0	0	0
T149	2956	0	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24804931	731	0	0
T23	448695	5	0	0
T50	0	2	0	0
T52	0	38	0	0
T59	0	159	0	0
T77	3123	0	0	0
T78	0	6	0	0
T93	0	11	0	0
T106	2333	0	0	0
T107	3219	0	0	0
T108	6919	0	0	0
T137	48762	0	0	0
T142	1200	0	0	0
T143	0	17	0	0
T145	0	7	0	0
T146	0	1	0	0
T147	4192	0	0	0
T148	6564	0	0	0
T149	2956	0	0	0
T150	0	11	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24804931	865	0	0
T23	448695	7	0	0
T50	0	20	0	0
T67	0	7	0	0
T77	3123	0	0	0
T78	0	6	0	0
T93	0	16	0	0
T106	2333	0	0	0
T107	3219	0	0	0
T108	6919	0	0	0
T137	48762	0	0	0
T142	1200	0	0	0
T143	0	8	0	0
T144	0	11	0	0
T145	0	4	0	0
T147	4192	0	0	0
T148	6564	0	0	0
T149	2956	0	0	0
T150	0	13	0	0
T151	0	5	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24804931	1333	0	0
T23	448695	7	0	0
T50	0	5	0	0
T52	0	73	0	0
T67	0	22	0	0
T77	3123	0	0	0
T78	0	28	0	0
T80	0	3	0	0
T93	0	12	0	0
T106	2333	0	0	0
T107	3219	0	0	0
T108	6919	0	0	0
T137	48762	0	0	0
T142	1200	0	0	0
T143	0	9	0	0
T145	0	3	0	0
T147	4192	0	0	0
T148	6564	0	0	0
T149	2956	0	0	0
T150	0	10	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24804931	745	0	0
T23	448695	8	0	0
T50	0	10	0	0
T67	0	6	0	0
T77	3123	0	0	0
T78	0	4	0	0
T93	0	12	0	0
T106	2333	0	0	0
T107	3219	0	0	0
T108	6919	0	0	0
T137	48762	0	0	0
T142	1200	0	0	0
T143	0	24	0	0
T145	0	1	0	0
T146	0	5	0	0
T147	4192	0	0	0
T148	6564	0	0	0
T149	2956	0	0	0
T150	0	15	0	0
T151	0	4	0	0