Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.62	100.00	83.87	99.21		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	72624645	145549	0	0
StatusRise_A	72624645	162530	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72624645	145549	0	0
T1	13392	16	0	0
T2	25347	54	0	0
T3	17835	75	0	0
T4	8607	12	0	0
T5	20796	48	0	0
T6	11949	32	0	0
T7	5985	9	0	0
T8	3264	3	0	0
T9	72069	230	0	0
T10	45618	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72624645	162530	0	0
T1	13392	18	0	0
T2	25347	60	0	0
T3	17835	78	0	0
T4	8607	15	0	0
T5	20796	50	0	0
T6	11949	34	0	0
T7	5985	11	0	0
T8	3264	6	0	0
T9	72069	232	0	0
T10	45618	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24208215	54176	0	0
StatusRise_A	24208215	60297	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	54176	0	0
T1	4464	7	0	0
T2	8449	18	0	0
T3	5945	25	0	0
T4	2869	4	0	0
T5	6932	17	0	0
T6	3983	12	0	0
T7	1995	4	0	0
T8	1088	1	0	0
T9	24023	88	0	0
T10	15206	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	60297	0	0
T1	4464	8	0	0
T2	8449	20	0	0
T3	5945	26	0	0
T4	2869	5	0	0
T5	6932	18	0	0
T6	3983	13	0	0
T7	1995	5	0	0
T8	1088	2	0	0
T9	24023	89	0	0
T10	15206	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24208215	54177	0	0
StatusRise_A	24208215	60298	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	54177	0	0
T1	4464	7	0	0
T2	8449	18	0	0
T3	5945	25	0	0
T4	2869	4	0	0
T5	6932	17	0	0
T6	3983	12	0	0
T7	1995	4	0	0
T8	1088	1	0	0
T9	24023	88	0	0
T10	15206	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	60298	0	0
T1	4464	8	0	0
T2	8449	20	0	0
T3	5945	26	0	0
T4	2869	5	0	0
T5	6932	18	0	0
T6	3983	13	0	0
T7	1995	5	0	0
T8	1088	2	0	0
T9	24023	89	0	0
T10	15206	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	24208215	37196	0	0
StatusRise_A	24208215	41935	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	37196	0	0
T1	4464	2	0	0
T2	8449	18	0	0
T3	5945	25	0	0
T4	2869	4	0	0
T5	6932	14	0	0
T6	3983	8	0	0
T7	1995	1	0	0
T8	1088	1	0	0
T9	24023	54	0	0
T10	15206	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24208215	41935	0	0
T1	4464	2	0	0
T2	8449	20	0	0
T3	5945	26	0	0
T4	2869	5	0	0
T5	6932	14	0	0
T6	3983	8	0	0
T7	1995	1	0	0
T8	1088	2	0	0
T9	24023	54	0	0
T10	15206	2	0	0